81a93fb3a9
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621 According to Intel SDM as below, the BIT0 should be treated as lock bit, and BIT1 should be treated as disable(1)/enable(0) bit. "11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b" Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>