6556224e1f
Our poor man's implementation of EnterS3WithImmediateWake () currently sets a high TPL level to disable interrupts, and simply calls the PEI entrypoint again after disabling the MMU. Unfortunately, this is not sufficient: DMA capable devices such as network controllers or USB controllers may still be enabled and writing to memory, e.g., in response to incoming network packets. So instead, do the full ExitBootServices() dance: allocate space and get the memory map, call ExitBootServices(), and in case it fails, get the memory map again and call ExitBootServices() again. This ensures that all cleanup related to DMA capable devices is performed before doing the warm reset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
35 lines
851 B
NASM
35 lines
851 B
NASM
;/** @file
|
|
; ResetSystemLib implementation using PSCI calls
|
|
;
|
|
; Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
|
|
;
|
|
; This program and the accompanying materials
|
|
; are licensed and made available under the terms and conditions of the BSD License
|
|
; which accompanies this distribution. The full text of the license may be found at
|
|
; http://opensource.org/licenses/bsd-license.php
|
|
;
|
|
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
;
|
|
;**/
|
|
|
|
INCLUDE AsmMacroExport.inc
|
|
PRESERVE8
|
|
|
|
IMPORT ArmDisableMmu
|
|
|
|
RVCT_ASM_EXPORT DisableMmuAndReenterPei
|
|
push {lr}
|
|
|
|
bl ArmDisableMmu
|
|
|
|
; no memory accesses after MMU and caches have been disabled
|
|
|
|
mov32 r0, FixedPcdGet64 (PcdFvBaseAddress)
|
|
blx r0
|
|
|
|
; never returns
|
|
nop
|
|
|
|
END
|