8aeb405466
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
/** @file
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RISC-V CSR encodings
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Copyright (c) 2019, Western Digital Corporation or its affiliates. All rights reserved.<BR>
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Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef RISCV_ENCODING_H_
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#define RISCV_ENCODING_H_
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#define MSTATUS_SIE 0x00000002UL
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#define MSTATUS_MIE 0x00000008UL
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#define MSTATUS_SPIE_SHIFT 5
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#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT)
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#define MSTATUS_UBE 0x00000040UL
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#define MSTATUS_MPIE 0x00000080UL
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#define MSTATUS_SPP_SHIFT 8
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#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT)
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#define MSTATUS_MPP_SHIFT 11
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#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT)
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#define SSTATUS_SIE MSTATUS_SIE
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#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT
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#define SSTATUS_SPIE MSTATUS_SPIE
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#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT
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#define SSTATUS_SPP MSTATUS_SPP
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#define IRQ_S_SOFT 1
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#define IRQ_VS_SOFT 2
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#define IRQ_M_SOFT 3
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#define IRQ_S_TIMER 5
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#define IRQ_VS_TIMER 6
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#define IRQ_M_TIMER 7
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#define IRQ_S_EXT 9
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#define IRQ_VS_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_S_GEXT 12
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#define IRQ_PMU_OVF 13
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#define MIP_SSIP (1UL << IRQ_S_SOFT)
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#define MIP_VSSIP (1UL << IRQ_VS_SOFT)
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#define MIP_MSIP (1UL << IRQ_M_SOFT)
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#define MIP_STIP (1UL << IRQ_S_TIMER)
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#define MIP_VSTIP (1UL << IRQ_VS_TIMER)
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#define MIP_MTIP (1UL << IRQ_M_TIMER)
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#define MIP_SEIP (1UL << IRQ_S_EXT)
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#define MIP_VSEIP (1UL << IRQ_VS_EXT)
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#define MIP_MEIP (1UL << IRQ_M_EXT)
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#define MIP_SGEIP (1UL << IRQ_S_GEXT)
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#define MIP_LCOFIP (1UL << IRQ_PMU_OVF)
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define PRV_U 0UL
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#define PRV_S 1UL
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#define PRV_M 3UL
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#define SATP64_MODE 0xF000000000000000ULL
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#define SATP64_ASID 0x0FFFF00000000000ULL
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#define SATP64_PPN 0x00000FFFFFFFFFFFULL
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#define SATP_MODE_OFF 0UL
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#define SATP_MODE_SV32 1UL
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#define SATP_MODE_SV39 8UL
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#define SATP_MODE_SV48 9UL
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#define SATP_MODE_SV57 10UL
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#define SATP_MODE_SV64 11UL
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#define SATP_MODE SATP64_MODE
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/* User Counters/Timers */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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/* Supervisor Trap Setup */
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#define CSR_SSTATUS 0x100
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#define CSR_SEDELEG 0x102
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#define CSR_SIDELEG 0x103
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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/* Supervisor Configuration */
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#define CSR_SENVCFG 0x10a
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/* Supervisor Trap Handling */
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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/* Supervisor Protection and Translation */
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#define CSR_SATP 0x180
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/* Trap/Exception Causes */
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#define CAUSE_MISALIGNED_FETCH 0x0
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#define CAUSE_FETCH_ACCESS 0x1
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#define CAUSE_ILLEGAL_INSTRUCTION 0x2
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#define CAUSE_BREAKPOINT 0x3
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#define CAUSE_MISALIGNED_LOAD 0x4
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#define CAUSE_LOAD_ACCESS 0x5
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#define CAUSE_MISALIGNED_STORE 0x6
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#define CAUSE_STORE_ACCESS 0x7
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#define CAUSE_USER_ECALL 0x8
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#define CAUSE_SUPERVISOR_ECALL 0x9
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#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa
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#define CAUSE_MACHINE_ECALL 0xb
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#define CAUSE_FETCH_PAGE_FAULT 0xc
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#define CAUSE_LOAD_PAGE_FAULT 0xd
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#define CAUSE_STORE_PAGE_FAULT 0xf
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#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
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#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
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#define CAUSE_VIRTUAL_INST_FAULT 0x16
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#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
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#endif
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