5343eab11a
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@927 6f19259b-4bc3-4df7-8a09-765794883524
435 lines
14 KiB
C
435 lines
14 KiB
C
/*++
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Copyright (c) 2006, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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VirtualMemory.c
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Abstract:
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x64 Virtual Memory Management Services in the form of an IA-32 driver.
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Used to establish a 1:1 Virtual to Physical Mapping that is required to
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enter Long Mode (x64 64-bit mode).
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While we make a 1:1 mapping (identity mapping) for all physical pages
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we still need to use the MTRR's to ensure that the cachability attirbutes
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for all memory regions is correct.
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The basic idea is to use 2MB page table entries where ever possible. If
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more granularity of cachability is required then 4K page tables are used.
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References:
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1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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--*/
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#include "VirtualMemory.h"
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x64_MTRR_VARIABLE_RANGE *mMTRRVariableRange;
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x64_MTRR_FIXED_RANGE mMTRRFixedRange;
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//
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// Physial memory limit values for each of the 11 fixed MTRRs
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//
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UINTN mFixedRangeLimit[] = {
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0x7FFFF, // Fixed MTRR #0 describes 0x00000..0x7FFFF
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0x9FFFF, // Fixed MTRR #1 describes 0x80000..0x9FFFF
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0xBFFFF, // Fixed MTRR #2 describes 0xA0000..0xBFFFF
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0xC7FFF, // Fixed MTRR #3 describes 0xC0000..0xC7FFF
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0xCFFFF, // Fixed MTRR #4 describes 0xC8000..0xCFFFF
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0xD7FFF, // Fixed MTRR #5 describes 0xD0000..0xD7FFF
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0xDFFFF, // Fixed MTRR #6 describes 0xD8000..0xDFFFF
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0xE7FFF, // Fixed MTRR #7 describes 0xE0000..0xE7FFF
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0xEFFFF, // Fixed MTRR #8 describes 0xE8000..0xEFFFF
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0xF7FFF, // Fixed MTRR #9 describes 0xF0000..0xF7FFF
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0xFFFFF // Fixed MTRR #10 describes 0xF8000..0xFFFFF
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};
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//
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// The size, in bits, of each of the 11 fixed MTRR.
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//
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UINTN mFixedRangeShift[] = {
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16, // Fixed MTRR #0 describes 8, 64 KB ranges
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14, // Fixed MTRR #1 describes 8, 16 KB ranges
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14, // Fixed MTRR #2 describes 8, 16 KB ranges
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12, // Fixed MTRR #3 describes 8, 4 KB ranges
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12, // Fixed MTRR #4 describes 8, 4 KB ranges
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12, // Fixed MTRR #5 describes 8, 4 KB ranges
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12, // Fixed MTRR #6 describes 8, 4 KB ranges
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12, // Fixed MTRR #7 describes 8, 4 KB ranges
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12, // Fixed MTRR #8 describes 8, 4 KB ranges
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12, // Fixed MTRR #9 describes 8, 4 KB ranges
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12 // Fixed MTRR #10 describes 8, 4 KB ranges
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};
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UINTN mPowerOf2[] = {
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1,
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2,
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4,
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8,
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16,
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32,
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64,
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128,
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256,
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512
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};
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x64_MTRR_MEMORY_TYPE
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EfiGetMTRRMemoryType (
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IN EFI_PHYSICAL_ADDRESS Address
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)
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/*++
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Routine Description:
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Retrieves the memory type from the MTRR that describes a physical address.
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Arguments:
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VariableRange - Set of Variable MTRRs
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FixedRange - Set of Fixed MTRRs
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Address - The physical address for which the MTRR memory type is being retrieved
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Returns:
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The MTRR Memory Type for the physical memory specified by Address.
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--*/
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{
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UINTN Index;
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UINTN TypeIndex;
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BOOLEAN Found;
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x64_MTRR_MEMORY_TYPE VariableType;
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EFI_PHYSICAL_ADDRESS MaskBase;
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EFI_PHYSICAL_ADDRESS PhysMask;
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//
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// If the MTRRs are disabled, then return the Uncached Memory Type
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//
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if (mMTRRFixedRange.DefaultType.Bits.E == 0) {
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return Uncached;
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}
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//
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// If the CPU supports Fixed MTRRs and the Fixed MTRRs are enabled, then
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// see if Address falls into one of the Fixed MTRRs
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//
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if (mMTRRFixedRange.Capabilities.Bits.FIX && mMTRRFixedRange.DefaultType.Bits.FE) {
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//
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// Loop though 11 fixed MTRRs
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//
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for (Index = 0; Index < 11; Index++) {
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//
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// Check for a matching range
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//
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if (Address <= mFixedRangeLimit[Index]) {
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//
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// Compute the offset address into the MTRR bu subtrating the base address of the MTRR
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//
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if (Index > 0) {
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Address = Address - (mFixedRangeLimit[Index-1] + 1);
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}
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//
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// Retrieve the index into the MTRR to extract the memory type. The range is 0..7
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//
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TypeIndex = (UINTN)RShiftU64 (Address, mFixedRangeShift[Index]);
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//
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// Retrieve and return the memory type for the matching range
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//
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return mMTRRFixedRange.Fixed[Index].Type[TypeIndex];
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}
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}
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}
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//
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// If Address was not found in a Fixed MTRR, then search the Variable MTRRs
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//
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for (Index = 0, Found = FALSE, VariableType = WriteBack; Index < mMTRRFixedRange.Capabilities.Bits.VCNT; Index++) {
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//
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// BugBug: __aullshr complier error
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//
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if ((mMTRRVariableRange[Index].PhysMask.Uint64 & 0x800) == 0x800) {
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//if (mMTRRVariableRange[Index].PhysMask.Bits.Valid == 1) {
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PhysMask = mMTRRVariableRange[Index].PhysMask.Uint64 & ~0xfff;
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MaskBase = PhysMask & (mMTRRVariableRange[Index].PhysBase.Uint64 & ~0xfff);
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if (MaskBase == (PhysMask & Address)) {
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//
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// Check to see how many matches we find
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//
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Found = TRUE;
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if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == Uncached) || (VariableType == Uncached)) {
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//
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// If any matching region uses UC, the memory region is UC
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//
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VariableType = Uncached;
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} else if ((mMTRRVariableRange[Index].PhysBase.Bits.Type == WriteThrough) || (VariableType == WriteThrough)){
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//
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// If it's WT and WB then set it to WT. If it's WT and other type it's undefined
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//
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VariableType = WriteThrough;
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} else {
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VariableType = mMTRRVariableRange[Index].PhysBase.Bits.Type;
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}
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}
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}
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}
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if (Found) {
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return VariableType;
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}
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//
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// Address was not found in the Fixed or Variable MTRRs, so return the default memory type
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//
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return mMTRRFixedRange.DefaultType.Bits.Type;
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}
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BOOLEAN
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CanNotUse2MBPage (
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IN EFI_PHYSICAL_ADDRESS BaseAddress
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)
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/*++
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Routine Description:
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Test to see if a 2MB aligned page has all the same attributes. If a 2MB page
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has more than one attibute type it needs to be split into multiple 4K pages.
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Arguments:
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BaseAddress - 2MB aligned address to check out
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Returns:
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TRUE - This 2MB address range (BaseAddress) can NOT be mapped by a 2MB page
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FALSE - This 2MB address range can be mapped by a 2MB page
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--*/
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{
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UINTN Index;
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x64_MTRR_MEMORY_TYPE MemoryType;
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x64_MTRR_MEMORY_TYPE PreviousMemoryType;
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//
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// Address needs to be 2MB aligned
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//
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ASSERT ((BaseAddress & 0x1fffff) == 0);
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PreviousMemoryType = -1;
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for (Index = 0; Index < 512; Index++, BaseAddress += 0x1000) {
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MemoryType = EfiGetMTRRMemoryType (BaseAddress);
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if ((Index != 0) && (MemoryType != PreviousMemoryType)) {
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return TRUE;
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}
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PreviousMemoryType = MemoryType;
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}
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//
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// All the pages had the same type
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//
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return FALSE;
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}
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VOID
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Convert2MBPageTo4KPages (
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IN x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB,
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IN EFI_PHYSICAL_ADDRESS PageAddress
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)
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/*++
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Routine Description:
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Convert a single 2MB page entry to 512 4K page entries. The attributes for
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the 4K pages are read from the MTRR registers.
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Arguments:
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PageDirectoryEntry2MB - Page directory entry for PageAddress
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PageAddress - 2MB algined address of region to convert
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Returns:
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None
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--*/
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{
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EFI_PHYSICAL_ADDRESS Address;
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x64_PAGE_DIRECTORY_ENTRY_4K *PageDirectoryEntry4k;
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x64_PAGE_TABLE_ENTRY_4K *PageTableEntry;
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UINTN Index1;
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//
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// Allocate the page table entry for the 4K pages
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//
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PageTableEntry = (x64_PAGE_TABLE_ENTRY_4K *) AllocatePages (1);
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ASSERT (PageTableEntry != NULL);
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//
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// Convert PageDirectoryEntry2MB into a 4K Page Directory
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//
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PageDirectoryEntry4k = (x64_PAGE_DIRECTORY_ENTRY_4K *)PageDirectoryEntry2MB;
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PageDirectoryEntry2MB->Uint64 = (UINT64)PageTableEntry;
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PageDirectoryEntry2MB->Bits.ReadWrite = 1;
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PageDirectoryEntry2MB->Bits.Present = 1;
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//
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// Fill in the 4K page entries with the attributes from the MTRRs
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//
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for (Index1 = 0, Address = PageAddress; Index1 < 512; Index1++, PageTableEntry++, Address += 0x1000) {
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PageTableEntry->Uint64 = (UINT64)Address;
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PageTableEntry->Bits.ReadWrite = 1;
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PageTableEntry->Bits.Present = 1;
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}
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}
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EFI_PHYSICAL_ADDRESS
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CreateIdentityMappingPageTables (
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IN UINT32 NumberOfProcessorPhysicalAddressBits
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)
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/*++
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Routine Description:
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping for physical memory from
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0 to 4GB. Memory above 4GB is not mapped. The MTRRs are used to
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determine the cachability of the physical memory regions
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Arguments:
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NumberOfProcessorPhysicalAddressBits - Number of processor address bits to use.
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Limits the number of page table entries
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to the physical address space.
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Returns:
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EFI_OUT_OF_RESOURCES There are not enough resources to allocate the Page Tables
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EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created
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--*/
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{
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EFI_PHYSICAL_ADDRESS PageAddress;
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UINTN Index;
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UINTN MaxBitsSupported;
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UINTN Index1;
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UINTN Index2;
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x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMapLevel4Entry;
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x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageMap;
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x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *PageDirectoryPointerEntry;
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x64_PAGE_TABLE_ENTRY_2M *PageDirectoryEntry2MB;
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//
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// Page Table structure 4 level 4K, 3 level 2MB.
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//
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// PageMapLevel4Entry : bits 47-39
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// PageDirectoryPointerEntry : bits 38-30
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// Page Table 2MB : PageDirectoryEntry2M : bits 29-21
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// Page Table 4K : PageDirectoryEntry4K : bits 29 - 21
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// PageTableEntry : bits 20 - 12
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//
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// Strategy is to map every thing in the processor address space using
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// 2MB pages. If more granularity is required the 2MB page will get
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// converted to set of 4K pages.
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//
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//
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// By architecture only one PageMapLevel4 exists - so lets allocate storgage for it.
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//
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PageMap = PageMapLevel4Entry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);
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ASSERT (PageMap != NULL);
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PageAddress = 0;
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//
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// The number of page-map Level-4 Offset entries is based on the number of
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// physical address bits. Less than equal to 38 bits only takes one entry.
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// 512 entries represents 48 address bits.
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//
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if (NumberOfProcessorPhysicalAddressBits <= 38) {
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MaxBitsSupported = 1;
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} else {
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MaxBitsSupported = mPowerOf2[NumberOfProcessorPhysicalAddressBits - 39];
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}
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for (Index = 0; Index < MaxBitsSupported; Index++, PageMapLevel4Entry++) {
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//
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// Each PML4 entry points to a page of Page Directory Pointer entires.
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// So lets allocate space for them and fill them in in the Index1 loop.
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//
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PageDirectoryPointerEntry = (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K *) AllocatePages (1);
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ASSERT (PageDirectoryPointerEntry != NULL);
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//
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// Make a PML4 Entry
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//
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PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;
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PageMapLevel4Entry->Bits.ReadWrite = 1;
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PageMapLevel4Entry->Bits.Present = 1;
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for (Index1 = 0; Index1 < 512; Index1++, PageDirectoryPointerEntry++) {
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//
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// Each Directory Pointer entries points to a page of Page Directory entires.
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// So lets allocate space for them and fill them in in the Index2 loop.
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//
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PageDirectoryEntry2MB = (x64_PAGE_TABLE_ENTRY_2M *) AllocatePages (1);
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ASSERT (PageDirectoryEntry2MB != NULL);
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//
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// Fill in a Page Directory Pointer Entries
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//
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PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry2MB;
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
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PageDirectoryPointerEntry->Bits.Present = 1;
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for (Index2 = 0; Index2 < 512; Index2++, PageDirectoryEntry2MB++, PageAddress += 0x200000) {
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//
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// Fill in the Page Directory entries
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//
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PageDirectoryEntry2MB->Uint64 = (UINT64)PageAddress;
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PageDirectoryEntry2MB->Bits.ReadWrite = 1;
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PageDirectoryEntry2MB->Bits.Present = 1;
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PageDirectoryEntry2MB->Bits.MustBe1 = 1;
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if (CanNotUse2MBPage (PageAddress)) {
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//
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// Check to see if all 2MB has the same mapping. If not convert
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// to 4K pages by adding the 4th level of page table entries
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//
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Convert2MBPageTo4KPages (PageDirectoryEntry2MB, PageAddress);
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}
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}
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}
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}
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//
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// For the PML4 entries we are not using fill in a null entry.
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// for now we just copy the first entry.
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//
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for (; Index < 512; Index++, PageMapLevel4Entry++) {
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// EfiCopyMem (PageMapLevel4Entry, PageMap, sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K));
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CopyMem (PageMapLevel4Entry,
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PageMap,
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sizeof (x64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K)
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);
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}
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return (EFI_PHYSICAL_ADDRESS)PageMap;
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}
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