7601b251fd
Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
22 lines
583 B
ArmAsm
22 lines
583 B
ArmAsm
//------------------------------------------------------------------------------
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//
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// RISC-V cache operation.
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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.align 3
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ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
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ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
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ASM_PFX(RiscVInvalidateInstCacheAsm):
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fence.i
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ret
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ASM_PFX(RiscVInvalidateDataCacheAsm):
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fence
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ret
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