7601b251fd
Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
15 lines
421 B
ArmAsm
15 lines
421 B
ArmAsm
//------------------------------------------------------------------------------
|
|
//
|
|
// CpuPause for RISC-V
|
|
//
|
|
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
|
|
//
|
|
// SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
//
|
|
//------------------------------------------------------------------------------
|
|
|
|
ASM_GLOBAL ASM_PFX(RiscVCpuPause)
|
|
ASM_PFX(RiscVCpuPause):
|
|
nop
|
|
ret
|