7601b251fd
Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
33 lines
929 B
ArmAsm
33 lines
929 B
ArmAsm
//------------------------------------------------------------------------------
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//
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// RISC-V Supervisor Mode interrupt enable/disable
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
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ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
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ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
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# define MSTATUS_SIE 0x00000002
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# define CSR_SSTATUS 0x100
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ASM_PFX(RiscVDisableSupervisorModeInterrupts):
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li a1, MSTATUS_SIE
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csrc CSR_SSTATUS, a1
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ret
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ASM_PFX(RiscVEnableSupervisorModeInterrupt):
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li a1, MSTATUS_SIE
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csrs CSR_SSTATUS, a1
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ret
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ASM_PFX(RiscVGetSupervisorModeInterrupts):
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csrr a0, CSR_SSTATUS
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andi a0, a0, MSTATUS_SIE
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ret
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