c86cd1e175
This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings library. All string routines are accelerated except ScanMem16, ScanMem32, ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few occurrences exist in the codebase) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
143 lines
4.9 KiB
ArmAsm
143 lines
4.9 KiB
ArmAsm
//
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// Copyright (c) 2013, Linaro Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the Linaro nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Assumptions:
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//
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// ARMv8-a, AArch64
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//
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// Parameters and result.
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#define src1 x0
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#define src2 x1
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#define limit x2
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#define result x0
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// Internal variables.
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#define data1 x3
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#define data1w w3
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#define data2 x4
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#define data2w w4
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#define diff x6
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#define endloop x7
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#define tmp1 x8
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#define tmp2 x9
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#define pos x11
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#define limit_wd x12
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#define mask x13
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.p2align 6
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ASM_GLOBAL ASM_PFX(InternalMemCompareMem)
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ASM_PFX(InternalMemCompareMem):
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eor tmp1, src1, src2
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tst tmp1, #7
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b.ne .Lmisaligned8
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ands tmp1, src1, #7
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b.ne .Lmutual_align
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add limit_wd, limit, #7
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lsr limit_wd, limit_wd, #3
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// Start of performance-critical section -- one 64B cache line.
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.Lloop_aligned:
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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.Lstart_realigned:
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subs limit_wd, limit_wd, #1
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eor diff, data1, data2 // Non-zero if differences found.
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csinv endloop, diff, xzr, ne // Last Dword or differences.
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cbz endloop, .Lloop_aligned
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// End of performance-critical section -- one 64B cache line.
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// Not reached the limit, must have found a diff.
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cbnz limit_wd, .Lnot_limit
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// Limit % 8 == 0 => all bytes significant.
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ands limit, limit, #7
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b.eq .Lnot_limit
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lsl limit, limit, #3 // Bits -> bytes.
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mov mask, #~0
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lsl mask, mask, limit
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bic data1, data1, mask
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bic data2, data2, mask
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orr diff, diff, mask
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.Lnot_limit:
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rev diff, diff
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rev data1, data1
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rev data2, data2
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// The MS-non-zero bit of DIFF marks either the first bit
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// that is different, or the end of the significant data.
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// Shifting left now will bring the critical information into the
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// top bits.
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clz pos, diff
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lsl data1, data1, pos
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lsl data2, data2, pos
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// But we need to zero-extend (char is unsigned) the value and then
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// perform a signed 32-bit subtraction.
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lsr data1, data1, #56
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sub result, data1, data2, lsr #56
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ret
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.Lmutual_align:
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// Sources are mutually aligned, but are not currently at an
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// alignment boundary. Round down the addresses and then mask off
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// the bytes that precede the start point.
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bic src1, src1, #7
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bic src2, src2, #7
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add limit, limit, tmp1 // Adjust the limit for the extra.
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lsl tmp1, tmp1, #3 // Bytes beyond alignment -> bits.
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ldr data1, [src1], #8
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neg tmp1, tmp1 // Bits to alignment -64.
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ldr data2, [src2], #8
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mov tmp2, #~0
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// Little-endian. Early bytes are at LSB.
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lsr tmp2, tmp2, tmp1 // Shift (tmp1 & 63).
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add limit_wd, limit, #7
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orr data1, data1, tmp2
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orr data2, data2, tmp2
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lsr limit_wd, limit_wd, #3
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b .Lstart_realigned
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.p2align 6
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.Lmisaligned8:
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sub limit, limit, #1
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1:
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// Perhaps we can do better than this.
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ldrb data1w, [src1], #1
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ldrb data2w, [src2], #1
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subs limit, limit, #1
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ccmp data1w, data2w, #0, cs // NZCV = 0b0000.
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b.eq 1b
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sub result, data1, data2
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ret
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