decaac5d0d
ARM uses the low order bit of a branch target address to decide in which execution mode (ARM or Thumb) a function needs to be called. In order for this to work across object files, ELF function symbols will have the low bit set if they were emitted in Thumb mode and cleared otherwise. This annotation is only emitted if the ELF symbols are annotated as function, since taking the address of some data symbol (e.g., a literal) should not produce a value with the low bit set, even if it appears in an object file containing Thumb code. This means that all functions coded in assembler must have this function annotation, or they may end up getting called in the wrong mode, crashing the program. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
67 lines
2.4 KiB
ArmAsm
67 lines
2.4 KiB
ArmAsm
//
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// Copyright (c) 2016, Linaro Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the Linaro nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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.text
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.thumb
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.syntax unified
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.align 5
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.type ASM_PFX(InternalMemCompareGuid), %function
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ASM_GLOBAL ASM_PFX(InternalMemCompareGuid)
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ASM_PFX(InternalMemCompareGuid):
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push {r4, lr}
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ldr r2, [r0]
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ldr r3, [r0, #4]
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ldr r4, [r0, #8]
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ldr r0, [r0, #12]
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cbz r1, 1f
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ldr ip, [r1]
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ldr lr, [r1, #4]
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cmp r2, ip
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it eq
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cmpeq.n r3, lr
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beq 0f
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movs r0, #0
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pop {r4, pc}
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0: ldr r2, [r1, #8]
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ldr r3, [r1, #12]
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cmp r4, r2
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it eq
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cmpeq.n r0, r3
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bne 2f
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movs r0, #1
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pop {r4, pc}
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1: orrs r2, r2, r3
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orrs r4, r4, r0
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movs r0, #1
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orrs r2, r2, r4
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2: it ne
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movne.n r0, #0
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pop {r4, pc}
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