9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
1263 lines
46 KiB
C
1263 lines
46 KiB
C
/** @file
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PCI configuration Library Services that do PCI configuration and also enable
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the PCI operations to be replayed during an S3 resume. This library class
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maps directly on top of the PciLib class.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/DebugLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Library/PciLib.h>
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#include <Library/S3PciLib.h>
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#define PCILIB_TO_COMMON_ADDRESS(Address) \
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((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((Address>>15) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((UINTN) (Address & 0xfff )))
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/**
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Saves a PCI configuration value to the boot script.
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This internal worker function saves a PCI configuration value in
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the S3 script to be replayed on S3 resume.
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If the saving process fails, then ASSERT().
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@param Width The width of PCI configuration.
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param Buffer The buffer containing value.
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**/
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VOID
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InternalSavePciWriteValueToBootScript (
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IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
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IN UINTN Address,
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IN VOID *Buffer
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)
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{
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RETURN_STATUS Status;
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Status = S3BootScriptSavePciCfgWrite (
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Width,
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PCILIB_TO_COMMON_ADDRESS(Address),
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1,
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Buffer
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);
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ASSERT (Status == RETURN_SUCCESS);
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}
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/**
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Saves an 8-bit PCI configuration value to the boot script.
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This internal worker function saves an 8-bit PCI configuration value in
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the S3 script to be replayed on S3 resume.
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If the saving process fails, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param Value The value saved to boot script.
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@return Value.
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**/
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UINT8
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InternalSavePciWrite8ValueToBootScript (
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IN UINTN Address,
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IN UINT8 Value
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)
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{
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InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);
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return Value;
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}
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/**
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Reads an 8-bit PCI configuration register and saves the value in the S3
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script to be replayed on S3 resume.
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Reads and returns the 8-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are
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serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@return The read value from the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciRead8 (
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IN UINTN Address
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciRead8 (Address));
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}
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/**
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Writes an 8-bit PCI configuration register and saves the value in the S3
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script to be replayed on S3 resume.
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Writes the 8-bit PCI configuration register specified by Address with the
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value specified by Value. Value is returned. This function must guarantee
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that all PCI read and write operations are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciWrite8 (
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IN UINTN Address,
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IN UINT8 Value
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciWrite8 (Address, Value));
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}
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/**
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Performs a bitwise OR of an 8-bit PCI configuration register with
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an 8-bit value and saves the value in the S3 script to be replayed on S3 resume.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise OR between the read result and the value specified by
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OrData, and writes the result to the 8-bit PCI configuration register
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specified by Address. The value written to the PCI configuration register is
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returned. This function must guarantee that all PCI read and write operations
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are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param OrData The value to OR with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciOr8 (
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IN UINTN Address,
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IN UINT8 OrData
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciOr8 (Address, OrData));
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}
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/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
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value and saves the value in the S3 script to be replayed on S3 resume.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND between the read result and the value specified by AndData, and
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writes the result to the 8-bit PCI configuration register specified by
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Address. The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are
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serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param AndData The value to AND with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciAnd8 (
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IN UINTN Address,
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IN UINT8 AndData
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciAnd8 (Address, AndData));
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}
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/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
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value, followed a bitwise OR with another 8-bit value and saves
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the value in the S3 script to be replayed on S3 resume.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND between the read result and the value specified by AndData,
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performs a bitwise OR between the result of the AND operation and
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the value specified by OrData, and writes the result to the 8-bit PCI
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configuration register specified by Address. The value written to the PCI
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configuration register is returned. This function must guarantee that all PCI
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read and write operations are serialized.
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If Address > 0x0FFFFFFF, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param AndData The value to AND with the PCI configuration register.
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@param OrData The value to OR with the result of the AND operation.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciAndThenOr8 (
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IN UINTN Address,
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IN UINT8 AndData,
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IN UINT8 OrData
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciAndThenOr8 (Address, AndData, OrData));
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}
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/**
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Reads a bit field of a PCI configuration register and saves the value in
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the S3 script to be replayed on S3 resume.
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Reads the bit field in an 8-bit PCI configuration register. The bit field is
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specified by the StartBit and the EndBit. The value of the bit field is
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returned.
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If Address > 0x0FFFFFFF, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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@param Address PCI configuration register to read.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@return The value of the bit field read from the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciBitFieldRead8 (
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IN UINTN Address,
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IN UINTN StartBit,
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IN UINTN EndBit
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldRead8 (Address, StartBit, EndBit));
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}
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/**
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Writes a bit field to a PCI configuration register and saves the value in
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the S3 script to be replayed on S3 resume.
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Writes Value to the bit field of the PCI configuration register. The bit
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field is specified by the StartBit and the EndBit. All other bits in the
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destination PCI configuration register are preserved. The new value of the
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8-bit register is returned.
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If Address > 0x0FFFFFFF, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param Value New value of the bit field.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciBitFieldWrite8 (
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IN UINTN Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 Value
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldWrite8 (Address, StartBit, EndBit, Value));
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}
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/**
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Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
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writes the result back to the bit field in the 8-bit port and saves the value
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in the S3 script to be replayed on S3 resume.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise OR between the read result and the value specified by
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OrData, and writes the result to the 8-bit PCI configuration register
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specified by Address. The value written to the PCI configuration register is
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returned. This function must guarantee that all PCI read and write operations
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are serialized. Extra left bits in OrData are stripped.
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If Address > 0x0FFFFFFF, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param OrData The value to OR with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciBitFieldOr8 (
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IN UINTN Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 OrData
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldOr8 (Address, StartBit, EndBit, OrData));
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}
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/**
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Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
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AND, and writes the result back to the bit field in the 8-bit register and
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saves the value in the S3 script to be replayed on S3 resume.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND between the read result and the value specified by AndData, and
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writes the result to the 8-bit PCI configuration register specified by
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Address. The value written to the PCI configuration register is returned.
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This function must guarantee that all PCI read and write operations are
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serialized. Extra left bits in AndData are stripped.
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If Address > 0x0FFFFFFF, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param AndData The value to AND with the PCI configuration register.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciBitFieldAnd8 (
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IN UINTN Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 AndData
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAnd8 (Address, StartBit, EndBit, AndData));
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}
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/**
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Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a
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bitwise OR, and writes the result back to the bit field in the
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8-bit port and saves the value in the S3 script to be replayed on S3 resume.
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Reads the 8-bit PCI configuration register specified by Address, performs a
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bitwise AND followed by a bitwise OR between the read result and
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the value specified by AndData, and writes the result to the 8-bit PCI
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configuration register specified by Address. The value written to the PCI
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configuration register is returned. This function must guarantee that all PCI
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read and write operations are serialized. Extra left bits in both AndData and
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OrData are stripped.
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If Address > 0x0FFFFFFF, then ASSERT().
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If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
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If EndBit is less than StartBit, then ASSERT().
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If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
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@param Address PCI configuration register to write.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
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Range 0..7.
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@param AndData The value to AND with the PCI configuration register.
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@param OrData The value to OR with the result of the AND operation.
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@return The value written back to the PCI configuration register.
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**/
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UINT8
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EFIAPI
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S3PciBitFieldAndThenOr8 (
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IN UINTN Address,
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IN UINTN StartBit,
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IN UINTN EndBit,
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IN UINT8 AndData,
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IN UINT8 OrData
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)
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{
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return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));
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}
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/**
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Saves a 16-bit PCI configuration value to the boot script.
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This internal worker function saves a 16-bit PCI configuration value in
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the S3 script to be replayed on S3 resume.
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If the saving process fails, then ASSERT().
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@param Value The value to write.
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@return Value.
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**/
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UINT16
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InternalSavePciWrite16ValueToBootScript (
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IN UINTN Address,
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IN UINT16 Value
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)
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{
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InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);
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return Value;
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}
|
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|
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/**
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Reads a 16-bit PCI configuration register and saves the value in the S3
|
|
script to be replayed on S3 resume.
|
|
|
|
Reads and returns the 16-bit PCI configuration register specified by Address.
|
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This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
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If Address > 0x0FFFFFFF, then ASSERT().
|
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If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
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@param Address Address that encodes the PCI Bus, Device, Function and
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Register.
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@return The read value from the PCI configuration register.
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**/
|
|
UINT16
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EFIAPI
|
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S3PciRead16 (
|
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IN UINTN Address
|
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)
|
|
{
|
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return InternalSavePciWrite16ValueToBootScript (Address, PciRead16 (Address));
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|
}
|
|
|
|
/**
|
|
Writes a 16-bit PCI configuration register and saves the value in the S3
|
|
script to be replayed on S3 resume.
|
|
|
|
Writes the 16-bit PCI configuration register specified by Address with the
|
|
value specified by Value. Value is returned. This function must guarantee
|
|
that all PCI read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
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Register.
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@param Value The value to write.
|
|
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@return The value written to the PCI configuration register.
|
|
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|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciWrite16 (
|
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IN UINTN Address,
|
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IN UINT16 Value
|
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)
|
|
{
|
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return InternalSavePciWrite16ValueToBootScript (Address, PciWrite16 (Address, Value));
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise OR of a 16-bit PCI configuration register with
|
|
a 16-bit value and saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 16-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
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@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciOr16 (
|
|
IN UINTN Address,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciOr16 (Address, OrData));
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
|
value and saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 16-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciAnd16 (
|
|
IN UINTN Address,
|
|
IN UINT16 AndData
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciAnd16 (Address, AndData));
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
|
|
value, followed a bitwise OR with another 16-bit value and saves
|
|
the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData,
|
|
performs a bitwise OR between the result of the AND operation and
|
|
the value specified by OrData, and writes the result to the 16-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciAndThenOr16 (
|
|
IN UINTN Address,
|
|
IN UINT16 AndData,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciAndThenOr16 (Address, AndData, OrData));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field of a PCI configuration register and saves the value in
|
|
the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the bit field in a 16-bit PCI configuration register. The bit field is
|
|
specified by the StartBit and the EndBit. The value of the bit field is
|
|
returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to read.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciBitFieldRead16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldRead16 (Address, StartBit, EndBit));
|
|
}
|
|
|
|
/**
|
|
Writes a bit field to a PCI configuration register and saves the value in
|
|
the S3 script to be replayed on S3 resume.
|
|
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
|
field is specified by the StartBit and the EndBit. All other bits in the
|
|
destination PCI configuration register are preserved. The new value of the
|
|
16-bit register is returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param Value New value of the bit field.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciBitFieldWrite16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 Value
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldWrite16 (Address, StartBit, EndBit, Value));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
|
|
writes the result back to the bit field in the 16-bit port and saves the value
|
|
in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 16-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized. Extra left bits in OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciBitFieldOr16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldOr16 (Address, StartBit, EndBit, OrData));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
|
|
AND, and writes the result back to the bit field in the 16-bit register and
|
|
saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 16-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized. Extra left bits in AndData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciBitFieldAnd16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 AndData
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAnd16 (Address, StartBit, EndBit, AndData));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a
|
|
bitwise OR, and writes the result back to the bit field in the
|
|
16-bit port and saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND followed by a bitwise OR between the read result and
|
|
the value specified by AndData, and writes the result to the 16-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in both AndData and
|
|
OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
If StartBit is greater than 15, then ASSERT().
|
|
If EndBit is greater than 15, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..15.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..15.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT16
|
|
EFIAPI
|
|
S3PciBitFieldAndThenOr16 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT16 AndData,
|
|
IN UINT16 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));
|
|
}
|
|
|
|
/**
|
|
Saves a 32-bit PCI configuration value to the boot script.
|
|
|
|
This internal worker function saves a 32-bit PCI configuration value in the S3 script
|
|
to be replayed on S3 resume.
|
|
|
|
If the saving process fails, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param Value The value to write.
|
|
|
|
@return Value.
|
|
|
|
**/
|
|
UINT32
|
|
InternalSavePciWrite32ValueToBootScript (
|
|
IN UINTN Address,
|
|
IN UINT32 Value
|
|
)
|
|
{
|
|
InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);
|
|
|
|
return Value;
|
|
}
|
|
|
|
/**
|
|
Reads a 32-bit PCI configuration register and saves the value in the S3
|
|
script to be replayed on S3 resume.
|
|
|
|
Reads and returns the 32-bit PCI configuration register specified by Address.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
|
|
@return The read value from the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciRead32 (
|
|
IN UINTN Address
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciRead32 (Address));
|
|
}
|
|
|
|
/**
|
|
Writes a 32-bit PCI configuration register and saves the value in the S3
|
|
script to be replayed on S3 resume.
|
|
|
|
Writes the 32-bit PCI configuration register specified by Address with the
|
|
value specified by Value. Value is returned. This function must guarantee
|
|
that all PCI read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param Value The value to write.
|
|
|
|
@return The value written to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciWrite32 (
|
|
IN UINTN Address,
|
|
IN UINT32 Value
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciWrite32 (Address, Value));
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise OR of a 32-bit PCI configuration register with
|
|
a 32-bit value and saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 32-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciOr32 (
|
|
IN UINTN Address,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciOr32 (Address, OrData));
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
|
value and saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 32-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciAnd32 (
|
|
IN UINTN Address,
|
|
IN UINT32 AndData
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciAnd32 (Address, AndData));
|
|
}
|
|
|
|
/**
|
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
|
|
value, followed a bitwise OR with another 32-bit value and saves
|
|
the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData,
|
|
performs a bitwise OR between the result of the AND operation and
|
|
the value specified by OrData, and writes the result to the 32-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
|
|
@param Address Address that encodes the PCI Bus, Device, Function and
|
|
Register.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciAndThenOr32 (
|
|
IN UINTN Address,
|
|
IN UINT32 AndData,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciAndThenOr32 (Address, AndData, OrData));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field of a PCI configuration register and saves the value in
|
|
the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the bit field in a 32-bit PCI configuration register. The bit field is
|
|
specified by the StartBit and the EndBit. The value of the bit field is
|
|
returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to read.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciBitFieldRead32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldRead32 (Address, StartBit, EndBit));
|
|
}
|
|
|
|
/**
|
|
Writes a bit field to a PCI configuration register and saves the value in
|
|
the S3 script to be replayed on S3 resume.
|
|
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
|
field is specified by the StartBit and the EndBit. All other bits in the
|
|
destination PCI configuration register are preserved. The new value of the
|
|
32-bit register is returned.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param Value New value of the bit field.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciBitFieldWrite32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 Value
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldWrite32 (Address, StartBit, EndBit, Value));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
|
|
writes the result back to the bit field in the 32-bit port and saves the value
|
|
in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise OR between the read result and the value specified by
|
|
OrData, and writes the result to the 32-bit PCI configuration register
|
|
specified by Address. The value written to the PCI configuration register is
|
|
returned. This function must guarantee that all PCI read and write operations
|
|
are serialized. Extra left bits in OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param OrData The value to OR with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciBitFieldOr32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldOr32 (Address, StartBit, EndBit, OrData));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
|
|
AND, and writes the result back to the bit field in the 32-bit register and
|
|
saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND between the read result and the value specified by AndData, and
|
|
writes the result to the 32-bit PCI configuration register specified by
|
|
Address. The value written to the PCI configuration register is returned.
|
|
This function must guarantee that all PCI read and write operations are
|
|
serialized. Extra left bits in AndData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciBitFieldAnd32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 AndData
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAnd32 (Address, StartBit, EndBit, AndData));
|
|
}
|
|
|
|
/**
|
|
Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a
|
|
bitwise OR, and writes the result back to the bit field in the
|
|
32-bit port and saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
|
bitwise AND followed by a bitwise OR between the read result and
|
|
the value specified by AndData, and writes the result to the 32-bit PCI
|
|
configuration register specified by Address. The value written to the PCI
|
|
configuration register is returned. This function must guarantee that all PCI
|
|
read and write operations are serialized. Extra left bits in both AndData and
|
|
OrData are stripped.
|
|
|
|
If Address > 0x0FFFFFFF, then ASSERT().
|
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
If StartBit is greater than 31, then ASSERT().
|
|
If EndBit is greater than 31, then ASSERT().
|
|
If EndBit is less than StartBit, then ASSERT().
|
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
|
|
@param Address PCI configuration register to write.
|
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
|
Range 0..31.
|
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
|
Range 0..31.
|
|
@param AndData The value to AND with the PCI configuration register.
|
|
@param OrData The value to OR with the result of the AND operation.
|
|
|
|
@return The value written back to the PCI configuration register.
|
|
|
|
**/
|
|
UINT32
|
|
EFIAPI
|
|
S3PciBitFieldAndThenOr32 (
|
|
IN UINTN Address,
|
|
IN UINTN StartBit,
|
|
IN UINTN EndBit,
|
|
IN UINT32 AndData,
|
|
IN UINT32 OrData
|
|
)
|
|
{
|
|
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));
|
|
}
|
|
|
|
/**
|
|
Reads a range of PCI configuration registers into a caller supplied buffer
|
|
and saves the value in the S3 script to be replayed on S3 resume.
|
|
|
|
Reads the range of PCI configuration registers specified by StartAddress and
|
|
Size into the buffer specified by Buffer. This function only allows the PCI
|
|
configuration registers from a single PCI function to be read. Size is
|
|
returned. When possible 32-bit PCI configuration read cycles are used to read
|
|
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
|
|
and 16-bit PCI configuration read cycles may be used at the beginning and the
|
|
end of the range.
|
|
|
|
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
|
@param StartAddress Starting address that encodes the PCI Bus, Device,
|
|
Function and Register.
|
|
@param Size Size in bytes of the transfer.
|
|
@param Buffer Pointer to a buffer receiving the data read.
|
|
|
|
@return Size
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
S3PciReadBuffer (
|
|
IN UINTN StartAddress,
|
|
IN UINTN Size,
|
|
OUT VOID *Buffer
|
|
)
|
|
{
|
|
RETURN_STATUS Status;
|
|
|
|
Status = S3BootScriptSavePciCfgWrite (
|
|
S3BootScriptWidthUint8,
|
|
PCILIB_TO_COMMON_ADDRESS (StartAddress),
|
|
PciReadBuffer (StartAddress, Size, Buffer),
|
|
Buffer
|
|
);
|
|
ASSERT (Status == RETURN_SUCCESS);
|
|
|
|
return Size;
|
|
}
|
|
|
|
/**
|
|
Copies the data in a caller supplied buffer to a specified range of PCI
|
|
configuration space and saves the value in the S3 script to be replayed on S3
|
|
resume.
|
|
|
|
Writes the range of PCI configuration registers specified by StartAddress and
|
|
Size from the buffer specified by Buffer. This function only allows the PCI
|
|
configuration registers from a single PCI function to be written. Size is
|
|
returned. When possible 32-bit PCI configuration write cycles are used to
|
|
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
|
|
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
|
|
and the end of the range.
|
|
|
|
If StartAddress > 0x0FFFFFFF, then ASSERT().
|
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
|
|
@param StartAddress Starting address that encodes the PCI Bus, Device,
|
|
Function and Register.
|
|
@param Size Size in bytes of the transfer.
|
|
@param Buffer Pointer to a buffer containing the data to write.
|
|
|
|
@return Size
|
|
|
|
**/
|
|
UINTN
|
|
EFIAPI
|
|
S3PciWriteBuffer (
|
|
IN UINTN StartAddress,
|
|
IN UINTN Size,
|
|
IN VOID *Buffer
|
|
)
|
|
{
|
|
RETURN_STATUS Status;
|
|
|
|
Status = S3BootScriptSavePciCfgWrite (
|
|
S3BootScriptWidthUint8,
|
|
PCILIB_TO_COMMON_ADDRESS (StartAddress),
|
|
PciWriteBuffer (StartAddress, Size, Buffer),
|
|
Buffer
|
|
);
|
|
ASSERT (Status == RETURN_SUCCESS);
|
|
|
|
return Size;
|
|
}
|