c357fd6a1f
The System Memory region might be out of the 32-bit memory space. This change has been validated on the FVP AArch64 model using 4GB of DRAM at 0x8_0000_0000: - # System Memory (2GB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + # System Memory (4GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 EFI Shell and Linux kernel boot successfully. Note: This change has not been validated on AArch32. I expect some early assembly code to not work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
81 lines
3.2 KiB
C
81 lines
3.2 KiB
C
/** @file
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* Header defining Versatile Express constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __ARM_VEXPRESS_H__
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#define __ARM_VEXPRESS_H__
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#include <VExpressMotherBoard.h>
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/***********************************************************************************
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// Platform Memory Map
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************************************************************************************/
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// Can be NOR0, NOR1, DRAM
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#define ARM_VE_REMAP_BASE 0x00000000
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#define ARM_VE_REMAP_SZ SIZE_64MB
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
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// NOR Flash 1
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// There is typo in the reference manual for the Base address of NOR Flash 1
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#define ARM_VE_SMB_NOR0_BASE 0x08000000
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#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
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// NOR Flash 2
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#define ARM_VE_SMB_NOR1_BASE 0x0C000000
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#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
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// SRAM
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#define ARM_VE_SMB_SRAM_BASE 0x2E000000
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#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
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// USB, Ethernet, VRAM
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#define ARM_VE_SMB_PERIPH_BASE 0x18000000
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#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
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#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
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// DRAM
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#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
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#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)
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// This can be any value since we only support motherboard PL111
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#define LCD_VRAM_CORE_TILE_BASE 0x00000000
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// On-chip peripherals (Snoop Control Unit etc...)
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#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000
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// Note: The TRM says not all the peripherals are implemented
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#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB
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// External AXI between daughterboards (Logic Tile)
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#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled
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#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
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/***********************************************************************************
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// Memory-mapped peripherals
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************************************************************************************/
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// SP810 Controller
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#undef SP810_CTRL_BASE
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#define SP810_CTRL_BASE 0x1C020000
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// PL111 Colour LCD Controller
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#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
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#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
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#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
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// VRAM offset for the PL111 Colour LCD Controller on the motherboard
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#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
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#endif
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