919a3a026c
This ensures the .type directive is used to mark them as function symbols Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
49 lines
1.6 KiB
ArmAsm
49 lines
1.6 KiB
ArmAsm
#========================================================================================
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http:#opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#=======================================================================================
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#include <AsmMacroIoLibV8.h>
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#include <Chipset/AArch64.h>
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#start of the code section
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.text
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.align 3
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GCC_ASM_EXPORT(SetupExceptionLevel1)
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GCC_ASM_EXPORT(SetupExceptionLevel2)
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// Setup EL1 while in EL1
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ASM_PFX(SetupExceptionLevel1):
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mov x5, x30 // Save LR
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mov x0, #CPACR_CP_FULL_ACCESS
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bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1
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ret x5
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// Setup EL2 while in EL2
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ASM_PFX(SetupExceptionLevel2):
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msr sctlr_el2, xzr
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mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
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// Send all interrupts to their respective Exception levels for EL2
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orr x0, x0, #(1 << 3) // Enable EL2 FIQ
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orr x0, x0, #(1 << 4) // Enable EL2 IRQ
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orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort
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msr hcr_el2, x0 // Write back our settings
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msr cptr_el2, xzr // Disable copro traps to EL2
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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