9d510e61fc
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
818 lines
25 KiB
C
818 lines
25 KiB
C
/** @file
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x64 Virtual Memory Management Services in the form of an IA-32 driver.
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Used to establish a 1:1 Virtual to Physical Mapping that is required to
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enter Long Mode (x64 64-bit mode).
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While we make a 1:1 mapping (identity mapping) for all physical pages
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we still need to use the MTRR's to ensure that the cachability attributes
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for all memory regions is correct.
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The basic idea is to use 2MB page table entries where ever possible. If
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more granularity of cachability is required then 4K page tables are used.
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References:
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1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "DxeIpl.h"
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#include "VirtualMemory.h"
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//
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// Global variable to keep track current available memory used as page table.
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//
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PAGE_TABLE_POOL *mPageTablePool = NULL;
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/**
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Clear legacy memory located at the first 4K-page, if available.
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This function traverses the whole HOB list to check if memory from 0 to 4095
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exists and has not been allocated, and then clear it if so.
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@param HobStart The start of HobList passed to DxeCore.
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**/
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VOID
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ClearFirst4KPage (
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IN VOID *HobStart
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)
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{
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EFI_PEI_HOB_POINTERS RscHob;
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EFI_PEI_HOB_POINTERS MemHob;
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BOOLEAN DoClear;
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RscHob.Raw = HobStart;
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MemHob.Raw = HobStart;
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DoClear = FALSE;
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//
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// Check if page 0 exists and free
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//
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while ((RscHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
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RscHob.Raw)) != NULL) {
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if (RscHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY &&
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RscHob.ResourceDescriptor->PhysicalStart == 0) {
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DoClear = TRUE;
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//
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// Make sure memory at 0-4095 has not been allocated.
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//
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while ((MemHob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION,
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MemHob.Raw)) != NULL) {
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if (MemHob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress
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< EFI_PAGE_SIZE) {
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DoClear = FALSE;
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break;
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}
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MemHob.Raw = GET_NEXT_HOB (MemHob);
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}
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break;
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}
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RscHob.Raw = GET_NEXT_HOB (RscHob);
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}
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if (DoClear) {
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DEBUG ((DEBUG_INFO, "Clearing first 4K-page!\r\n"));
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SetMem (NULL, EFI_PAGE_SIZE, 0);
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}
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return;
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}
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/**
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Return configure status of NULL pointer detection feature.
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@return TRUE NULL pointer detection feature is enabled
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@return FALSE NULL pointer detection feature is disabled
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**/
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BOOLEAN
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IsNullDetectionEnabled (
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VOID
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)
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{
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return ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT0) != 0);
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}
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/**
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The function will check if Execute Disable Bit is available.
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@retval TRUE Execute Disable Bit is available.
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@retval FALSE Execute Disable Bit is not available.
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**/
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BOOLEAN
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IsExecuteDisableBitAvailable (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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BOOLEAN Available;
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Available = FALSE;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT20) != 0) {
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//
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// Bit 20: Execute Disable Bit available.
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//
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Available = TRUE;
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}
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}
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return Available;
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}
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/**
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Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.
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@retval TRUE IA32_EFER.NXE should be enabled.
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@retval FALSE IA32_EFER.NXE should not be enabled.
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**/
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BOOLEAN
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IsEnableNonExecNeeded (
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VOID
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)
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{
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if (!IsExecuteDisableBitAvailable ()) {
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return FALSE;
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}
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//
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// XD flag (BIT63) in page table entry is only valid if IA32_EFER.NXE is set.
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// Features controlled by Following PCDs need this feature to be enabled.
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//
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return (PcdGetBool (PcdSetNxForStack) ||
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PcdGet64 (PcdDxeNxMemoryProtectionPolicy) != 0 ||
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PcdGet32 (PcdImageProtectionPolicy) != 0);
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}
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/**
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Enable Execute Disable Bit.
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**/
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VOID
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EnableExecuteDisableBit (
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VOID
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)
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{
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UINT64 MsrRegisters;
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MsrRegisters = AsmReadMsr64 (0xC0000080);
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MsrRegisters |= BIT11;
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AsmWriteMsr64 (0xC0000080, MsrRegisters);
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}
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/**
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The function will check if page table entry should be splitted to smaller
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granularity.
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@param Address Physical memory address.
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@param Size Size of the given physical memory.
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@param StackBase Base address of stack.
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@param StackSize Size of stack.
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@retval TRUE Page table should be split.
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@retval FALSE Page table should not be split.
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**/
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BOOLEAN
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ToSplitPageTable (
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IN EFI_PHYSICAL_ADDRESS Address,
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IN UINTN Size,
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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)
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{
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if (IsNullDetectionEnabled () && Address == 0) {
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return TRUE;
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}
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if (PcdGetBool (PcdCpuStackGuard)) {
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if (StackBase >= Address && StackBase < (Address + Size)) {
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return TRUE;
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}
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}
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if (PcdGetBool (PcdSetNxForStack)) {
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if ((Address < StackBase + StackSize) && ((Address + Size) > StackBase)) {
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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Initialize a buffer pool for page table use only.
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To reduce the potential split operation on page table, the pages reserved for
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page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and
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at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always
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initialized with number of pages greater than or equal to the given PoolPages.
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Once the pages in the pool are used up, this method should be called again to
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reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. But usually this won't
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happen in practice.
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@param PoolPages The least page number of the pool to be created.
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@retval TRUE The pool is initialized successfully.
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@retval FALSE The memory is out of resource.
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**/
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BOOLEAN
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InitializePageTablePool (
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IN UINTN PoolPages
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)
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{
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VOID *Buffer;
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//
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// Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
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// header.
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//
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PoolPages += 1; // Add one page for header.
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PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *
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PAGE_TABLE_POOL_UNIT_PAGES;
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Buffer = AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT);
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if (Buffer == NULL) {
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DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n"));
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return FALSE;
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}
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//
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// Link all pools into a list for easier track later.
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//
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if (mPageTablePool == NULL) {
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mPageTablePool = Buffer;
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mPageTablePool->NextPool = mPageTablePool;
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} else {
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((PAGE_TABLE_POOL *)Buffer)->NextPool = mPageTablePool->NextPool;
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mPageTablePool->NextPool = Buffer;
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mPageTablePool = Buffer;
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}
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//
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// Reserve one page for pool header.
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//
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mPageTablePool->FreePages = PoolPages - 1;
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mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);
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return TRUE;
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}
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/**
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This API provides a way to allocate memory for page table.
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This API can be called more than once to allocate memory for page tables.
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Allocates the number of 4KB pages and returns a pointer to the allocated
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buffer. The buffer returned is aligned on a 4KB boundary.
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If Pages is 0, then NULL is returned.
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If there is not enough memory remaining to satisfy the request, then NULL is
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returned.
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@param Pages The number of 4 KB pages to allocate.
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@return A pointer to the allocated buffer or NULL if allocation fails.
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**/
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VOID *
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AllocatePageTableMemory (
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IN UINTN Pages
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)
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{
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VOID *Buffer;
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if (Pages == 0) {
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return NULL;
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}
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//
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// Renew the pool if necessary.
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//
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if (mPageTablePool == NULL ||
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Pages > mPageTablePool->FreePages) {
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if (!InitializePageTablePool (Pages)) {
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return NULL;
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}
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}
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Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;
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mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages);
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mPageTablePool->FreePages -= Pages;
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return Buffer;
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}
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/**
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Split 2M page to 4K.
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@param[in] PhysicalAddress Start physical address the 2M page covered.
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@param[in, out] PageEntry2M Pointer to 2M page entry.
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@param[in] StackBase Stack base address.
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@param[in] StackSize Stack size.
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**/
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VOID
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Split2MPageTo4K (
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IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
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IN OUT UINT64 *PageEntry2M,
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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)
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{
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EFI_PHYSICAL_ADDRESS PhysicalAddress4K;
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UINTN IndexOfPageTableEntries;
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PAGE_TABLE_4K_ENTRY *PageTableEntry;
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UINT64 AddressEncMask;
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//
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// Make sure AddressEncMask is contained to smallest supported address field
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//
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AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
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PageTableEntry = AllocatePageTableMemory (1);
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ASSERT (PageTableEntry != NULL);
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//
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// Fill in 2M page entry.
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//
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*PageEntry2M = (UINT64) (UINTN) PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
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PhysicalAddress4K = PhysicalAddress;
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for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) {
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//
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// Fill in the Page Table entries
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//
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PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;
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PageTableEntry->Bits.ReadWrite = 1;
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if ((IsNullDetectionEnabled () && PhysicalAddress4K == 0) ||
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(PcdGetBool (PcdCpuStackGuard) && PhysicalAddress4K == StackBase)) {
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PageTableEntry->Bits.Present = 0;
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} else {
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PageTableEntry->Bits.Present = 1;
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}
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if (PcdGetBool (PcdSetNxForStack)
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&& (PhysicalAddress4K >= StackBase)
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&& (PhysicalAddress4K < StackBase + StackSize)) {
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//
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// Set Nx bit for stack.
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//
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PageTableEntry->Bits.Nx = 1;
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}
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}
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}
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/**
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Split 1G page to 2M.
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@param[in] PhysicalAddress Start physical address the 1G page covered.
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@param[in, out] PageEntry1G Pointer to 1G page entry.
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@param[in] StackBase Stack base address.
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@param[in] StackSize Stack size.
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**/
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VOID
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Split1GPageTo2M (
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IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
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IN OUT UINT64 *PageEntry1G,
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IN EFI_PHYSICAL_ADDRESS StackBase,
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IN UINTN StackSize
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)
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{
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EFI_PHYSICAL_ADDRESS PhysicalAddress2M;
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UINTN IndexOfPageDirectoryEntries;
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PAGE_TABLE_ENTRY *PageDirectoryEntry;
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UINT64 AddressEncMask;
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//
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// Make sure AddressEncMask is contained to smallest supported address field
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//
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AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
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PageDirectoryEntry = AllocatePageTableMemory (1);
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ASSERT (PageDirectoryEntry != NULL);
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//
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// Fill in 1G page entry.
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//
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*PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
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PhysicalAddress2M = PhysicalAddress;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {
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if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSize)) {
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//
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// Need to split this 2M page that covers NULL or stack range.
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//
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Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);
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} else {
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//
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// Fill in the Page Directory entries
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//
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PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M | AddressEncMask;
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PageDirectoryEntry->Bits.ReadWrite = 1;
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PageDirectoryEntry->Bits.Present = 1;
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PageDirectoryEntry->Bits.MustBe1 = 1;
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}
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}
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}
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/**
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Set one page of page table pool memory to be read-only.
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@param[in] PageTableBase Base address of page table (CR3).
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@param[in] Address Start address of a page to be set as read-only.
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@param[in] Level4Paging Level 4 paging flag.
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**/
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VOID
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SetPageTablePoolReadOnly (
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IN UINTN PageTableBase,
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IN EFI_PHYSICAL_ADDRESS Address,
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IN BOOLEAN Level4Paging
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)
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{
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UINTN Index;
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UINTN EntryIndex;
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UINT64 AddressEncMask;
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EFI_PHYSICAL_ADDRESS PhysicalAddress;
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UINT64 *PageTable;
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UINT64 *NewPageTable;
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UINT64 PageAttr;
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UINT64 LevelSize[5];
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UINT64 LevelMask[5];
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UINTN LevelShift[5];
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UINTN Level;
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UINT64 PoolUnitSize;
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ASSERT (PageTableBase != 0);
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//
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// Since the page table is always from page table pool, which is always
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// located at the boundary of PcdPageTablePoolAlignment, we just need to
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// set the whole pool unit to be read-only.
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//
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Address = Address & PAGE_TABLE_POOL_ALIGN_MASK;
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LevelShift[1] = PAGING_L1_ADDRESS_SHIFT;
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LevelShift[2] = PAGING_L2_ADDRESS_SHIFT;
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LevelShift[3] = PAGING_L3_ADDRESS_SHIFT;
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LevelShift[4] = PAGING_L4_ADDRESS_SHIFT;
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LevelMask[1] = PAGING_4K_ADDRESS_MASK_64;
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LevelMask[2] = PAGING_2M_ADDRESS_MASK_64;
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LevelMask[3] = PAGING_1G_ADDRESS_MASK_64;
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LevelMask[4] = PAGING_1G_ADDRESS_MASK_64;
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LevelSize[1] = SIZE_4KB;
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LevelSize[2] = SIZE_2MB;
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LevelSize[3] = SIZE_1GB;
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LevelSize[4] = SIZE_512GB;
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AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
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PAGING_1G_ADDRESS_MASK_64;
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PageTable = (UINT64 *)(UINTN)PageTableBase;
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PoolUnitSize = PAGE_TABLE_POOL_UNIT_SIZE;
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for (Level = (Level4Paging) ? 4 : 3; Level > 0; --Level) {
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Index = ((UINTN)RShiftU64 (Address, LevelShift[Level]));
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Index &= PAGING_PAE_INDEX_MASK;
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PageAttr = PageTable[Index];
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if ((PageAttr & IA32_PG_PS) == 0) {
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//
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// Go to next level of table.
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//
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PageTable = (UINT64 *)(UINTN)(PageAttr & ~AddressEncMask &
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PAGING_4K_ADDRESS_MASK_64);
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continue;
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}
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if (PoolUnitSize >= LevelSize[Level]) {
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//
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// Clear R/W bit if current page granularity is not larger than pool unit
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// size.
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//
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if ((PageAttr & IA32_PG_RW) != 0) {
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while (PoolUnitSize > 0) {
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//
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// PAGE_TABLE_POOL_UNIT_SIZE and PAGE_TABLE_POOL_ALIGNMENT are fit in
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// one page (2MB). Then we don't need to update attributes for pages
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// crossing page directory. ASSERT below is for that purpose.
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//
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ASSERT (Index < EFI_PAGE_SIZE/sizeof (UINT64));
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PageTable[Index] &= ~(UINT64)IA32_PG_RW;
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PoolUnitSize -= LevelSize[Level];
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++Index;
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}
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}
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break;
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} else {
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//
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// The smaller granularity of page must be needed.
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//
|
|
ASSERT (Level > 1);
|
|
|
|
NewPageTable = AllocatePageTableMemory (1);
|
|
ASSERT (NewPageTable != NULL);
|
|
|
|
PhysicalAddress = PageAttr & LevelMask[Level];
|
|
for (EntryIndex = 0;
|
|
EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64);
|
|
++EntryIndex) {
|
|
NewPageTable[EntryIndex] = PhysicalAddress | AddressEncMask |
|
|
IA32_PG_P | IA32_PG_RW;
|
|
if (Level > 2) {
|
|
NewPageTable[EntryIndex] |= IA32_PG_PS;
|
|
}
|
|
PhysicalAddress += LevelSize[Level - 1];
|
|
}
|
|
|
|
PageTable[Index] = (UINT64)(UINTN)NewPageTable | AddressEncMask |
|
|
IA32_PG_P | IA32_PG_RW;
|
|
PageTable = NewPageTable;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
Prevent the memory pages used for page table from been overwritten.
|
|
|
|
@param[in] PageTableBase Base address of page table (CR3).
|
|
@param[in] Level4Paging Level 4 paging flag.
|
|
|
|
**/
|
|
VOID
|
|
EnablePageTableProtection (
|
|
IN UINTN PageTableBase,
|
|
IN BOOLEAN Level4Paging
|
|
)
|
|
{
|
|
PAGE_TABLE_POOL *HeadPool;
|
|
PAGE_TABLE_POOL *Pool;
|
|
UINT64 PoolSize;
|
|
EFI_PHYSICAL_ADDRESS Address;
|
|
|
|
if (mPageTablePool == NULL) {
|
|
return;
|
|
}
|
|
|
|
//
|
|
// Disable write protection, because we need to mark page table to be write
|
|
// protected.
|
|
//
|
|
AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
|
|
|
|
//
|
|
// SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
|
|
// remember original one in advance.
|
|
//
|
|
HeadPool = mPageTablePool;
|
|
Pool = HeadPool;
|
|
do {
|
|
Address = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool;
|
|
PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);
|
|
|
|
//
|
|
// The size of one pool must be multiple of PAGE_TABLE_POOL_UNIT_SIZE, which
|
|
// is one of page size of the processor (2MB by default). Let's apply the
|
|
// protection to them one by one.
|
|
//
|
|
while (PoolSize > 0) {
|
|
SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging);
|
|
Address += PAGE_TABLE_POOL_UNIT_SIZE;
|
|
PoolSize -= PAGE_TABLE_POOL_UNIT_SIZE;
|
|
}
|
|
|
|
Pool = Pool->NextPool;
|
|
} while (Pool != HeadPool);
|
|
|
|
//
|
|
// Enable write protection, after page table attribute updated.
|
|
//
|
|
AsmWriteCr0 (AsmReadCr0() | CR0_WP);
|
|
}
|
|
|
|
/**
|
|
Allocates and fills in the Page Directory and Page Table Entries to
|
|
establish a 1:1 Virtual to Physical mapping.
|
|
|
|
@param[in] StackBase Stack base address.
|
|
@param[in] StackSize Stack size.
|
|
|
|
@return The address of 4 level page map.
|
|
|
|
**/
|
|
UINTN
|
|
CreateIdentityMappingPageTables (
|
|
IN EFI_PHYSICAL_ADDRESS StackBase,
|
|
IN UINTN StackSize
|
|
)
|
|
{
|
|
UINT32 RegEax;
|
|
UINT32 RegEdx;
|
|
UINT8 PhysicalAddressBits;
|
|
EFI_PHYSICAL_ADDRESS PageAddress;
|
|
UINTN IndexOfPml4Entries;
|
|
UINTN IndexOfPdpEntries;
|
|
UINTN IndexOfPageDirectoryEntries;
|
|
UINT32 NumberOfPml4EntriesNeeded;
|
|
UINT32 NumberOfPdpEntriesNeeded;
|
|
PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
|
|
PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
|
|
PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
|
|
PAGE_TABLE_ENTRY *PageDirectoryEntry;
|
|
UINTN TotalPagesNum;
|
|
UINTN BigPageAddress;
|
|
VOID *Hob;
|
|
BOOLEAN Page1GSupport;
|
|
PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
|
|
UINT64 AddressEncMask;
|
|
|
|
//
|
|
// Make sure AddressEncMask is contained to smallest supported address field
|
|
//
|
|
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
|
|
|
|
Page1GSupport = FALSE;
|
|
if (PcdGetBool(PcdUse1GPageTable)) {
|
|
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
|
|
if (RegEax >= 0x80000001) {
|
|
AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
|
|
if ((RegEdx & BIT26) != 0) {
|
|
Page1GSupport = TRUE;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Get physical address bits supported.
|
|
//
|
|
Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
|
|
if (Hob != NULL) {
|
|
PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
|
|
} else {
|
|
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
|
|
if (RegEax >= 0x80000008) {
|
|
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
|
|
PhysicalAddressBits = (UINT8) RegEax;
|
|
} else {
|
|
PhysicalAddressBits = 36;
|
|
}
|
|
}
|
|
|
|
//
|
|
// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
|
|
//
|
|
ASSERT (PhysicalAddressBits <= 52);
|
|
if (PhysicalAddressBits > 48) {
|
|
PhysicalAddressBits = 48;
|
|
}
|
|
|
|
//
|
|
// Calculate the table entries needed.
|
|
//
|
|
if (PhysicalAddressBits <= 39 ) {
|
|
NumberOfPml4EntriesNeeded = 1;
|
|
NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));
|
|
} else {
|
|
NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));
|
|
NumberOfPdpEntriesNeeded = 512;
|
|
}
|
|
|
|
//
|
|
// Pre-allocate big pages to avoid later allocations.
|
|
//
|
|
if (!Page1GSupport) {
|
|
TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
|
|
} else {
|
|
TotalPagesNum = NumberOfPml4EntriesNeeded + 1;
|
|
}
|
|
BigPageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);
|
|
ASSERT (BigPageAddress != 0);
|
|
|
|
//
|
|
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
|
|
//
|
|
PageMap = (VOID *) BigPageAddress;
|
|
BigPageAddress += SIZE_4KB;
|
|
|
|
PageMapLevel4Entry = PageMap;
|
|
PageAddress = 0;
|
|
for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {
|
|
//
|
|
// Each PML4 entry points to a page of Page Directory Pointer entires.
|
|
// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
|
|
//
|
|
PageDirectoryPointerEntry = (VOID *) BigPageAddress;
|
|
BigPageAddress += SIZE_4KB;
|
|
|
|
//
|
|
// Make a PML4 Entry
|
|
//
|
|
PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;
|
|
PageMapLevel4Entry->Bits.ReadWrite = 1;
|
|
PageMapLevel4Entry->Bits.Present = 1;
|
|
|
|
if (Page1GSupport) {
|
|
PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;
|
|
|
|
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
|
|
if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize)) {
|
|
Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize);
|
|
} else {
|
|
//
|
|
// Fill in the Page Directory entries
|
|
//
|
|
PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
|
|
PageDirectory1GEntry->Bits.ReadWrite = 1;
|
|
PageDirectory1GEntry->Bits.Present = 1;
|
|
PageDirectory1GEntry->Bits.MustBe1 = 1;
|
|
}
|
|
}
|
|
} else {
|
|
for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
|
|
//
|
|
// Each Directory Pointer entries points to a page of Page Directory entires.
|
|
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
|
|
//
|
|
PageDirectoryEntry = (VOID *) BigPageAddress;
|
|
BigPageAddress += SIZE_4KB;
|
|
|
|
//
|
|
// Fill in a Page Directory Pointer Entries
|
|
//
|
|
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;
|
|
PageDirectoryPointerEntry->Bits.ReadWrite = 1;
|
|
PageDirectoryPointerEntry->Bits.Present = 1;
|
|
|
|
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
|
|
if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSize)) {
|
|
//
|
|
// Need to split this 2M page that covers NULL or stack range.
|
|
//
|
|
Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);
|
|
} else {
|
|
//
|
|
// Fill in the Page Directory entries
|
|
//
|
|
PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
|
|
PageDirectoryEntry->Bits.ReadWrite = 1;
|
|
PageDirectoryEntry->Bits.Present = 1;
|
|
PageDirectoryEntry->Bits.MustBe1 = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
|
|
ZeroMem (
|
|
PageDirectoryPointerEntry,
|
|
sizeof(PAGE_MAP_AND_DIRECTORY_POINTER)
|
|
);
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// For the PML4 entries we are not using fill in a null entry.
|
|
//
|
|
for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {
|
|
ZeroMem (
|
|
PageMapLevel4Entry,
|
|
sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
|
|
);
|
|
}
|
|
|
|
//
|
|
// Protect the page table by marking the memory used for page table to be
|
|
// read-only.
|
|
//
|
|
EnablePageTableProtection ((UINTN)PageMap, TRUE);
|
|
|
|
//
|
|
// Set IA32_EFER.NXE if necessary.
|
|
//
|
|
if (IsEnableNonExecNeeded ()) {
|
|
EnableExecuteDisableBit ();
|
|
}
|
|
|
|
return (UINTN)PageMap;
|
|
}
|
|
|