93ff7a4e8e
When CCIDX is supported, the Current Cache Size ID Register contains data above 32 bits: namely the number of sets. Avoid truncating this by returning a UINTN instead of UINT32. On AARCH32, the expanded number of sets data can be read via the CCSIDR2 register. Also, add Doxygen comments for the function. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
82 lines
2.8 KiB
C
82 lines
2.8 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __ARM_LIB_PRIVATE_H__
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#define __ARM_LIB_PRIVATE_H__
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#define CACHE_SIZE_4_KB (3UL)
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#define CACHE_SIZE_8_KB (4UL)
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#define CACHE_SIZE_16_KB (5UL)
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#define CACHE_SIZE_32_KB (6UL)
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#define CACHE_SIZE_64_KB (7UL)
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#define CACHE_SIZE_128_KB (8UL)
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#define CACHE_ASSOCIATIVITY_DIRECT (0UL)
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#define CACHE_ASSOCIATIVITY_4_WAY (2UL)
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#define CACHE_ASSOCIATIVITY_8_WAY (3UL)
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#define CACHE_PRESENT (0UL)
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#define CACHE_NOT_PRESENT (1UL)
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#define CACHE_LINE_LENGTH_32_BYTES (2UL)
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#define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)
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#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)
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#define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
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#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
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#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
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#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
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#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
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#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
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#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
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#define CACHE_TYPE_WRITE_BACK (0x0EUL)
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#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
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#define CACHE_ARCHITECTURE_UNIFIED (0UL)
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#define CACHE_ARCHITECTURE_SEPARATE (1UL)
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VOID
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CPSRMaskInsert (
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IN UINT32 Mask,
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IN UINT32 Value
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);
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UINT32
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CPSRRead (
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VOID
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);
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/** Reads the CCSIDR register for the specified cache.
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@param CSSELR The CSSELR cache selection register value.
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@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
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Returns the contents of the CCSIDR register in AARCH32 mode.
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**/
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UINTN
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ReadCCSIDR (
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IN UINT32 CSSELR
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);
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UINT32
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ReadCLIDR (
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VOID
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);
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#endif // __ARM_LIB_PRIVATE_H__
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