ebf4ef4d25
Removed MBI Device, which is not necessary for MinnowBoard Max, from ACPI DSDT Table per Windows team's request. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17101 6f19259b-4bc3-4df7-8a09-765794883524
710 lines
19 KiB
Plaintext
710 lines
19 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;
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;
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; This program and the accompanying materials are licensed and made available under
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; the terms and conditions of the BSD License that accompanies this distribution.
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; The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;* *;
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;* *;
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;**************************************************************************/
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// Define the following External variables to prevent a WARNING when
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// using ASL.EXE and an ERROR when using IASL.EXE.
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External(PDC0)
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External(PDC1)
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External(PDC2)
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External(PDC3)
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External(CFGD)
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External(\_PR.CPU0._PPC, IntObj)
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External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj)
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External(\_SB.STR3, DeviceObj)
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External(\_SB.I2C1.BATC, DeviceObj)
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External(\_SB.DPTF, DeviceObj)
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External(\_SB.TCHG, DeviceObj)
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External(\_SB.IAOE.PTSL)
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External(\_SB.IAOE.WKRS)
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//
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// Create a Global MUTEX.
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//
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Mutex(MUTX,0)
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// Port 80h Update:
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// Update 8 bits of the 32-bit Port 80h.
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//
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// Arguments:
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// Arg0: 0 = Write Port 80h, Bits 7:0 Only.
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// 1 = Write Port 80h, Bits 15:8 Only.
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// 2 = Write Port 80h, Bits 23:16 Only.
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// 3 = Write Port 80h, Bits 31:24 Only.
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// Arg1: 8-bit Value to write
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//
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// Return Value:
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// None
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Method(P8XH,2,Serialized)
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{
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If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0.
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{
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Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
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}
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If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8.
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{
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Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
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}
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If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16.
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{
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Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
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}
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If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24.
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{
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Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
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}
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}
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//
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// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
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//
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OperationRegion (SPRT, SystemIO, 0xB2, 2)
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Field (SPRT, ByteAcc, Lock, Preserve)
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{
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SSMP, 8
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}
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// The _PIC Control Method is optional for ACPI design. It allows the
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// OS to inform the ASL code which interrupt controller is being used,
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// the 8259 or APIC. The reference code in this document will address
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// PCI IRQ Routing and resource allocation for both cases.
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//
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// The values passed into _PIC are:
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// 0 = 8259
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// 1 = IOAPIC
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Method(\_PIC,1)
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{
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Store(Arg0,GPIC)
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Store(Arg0,PICM)
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}
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OperationRegion(SWC0, SystemIO, 0x610, 0x0F)
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Field(SWC0, ByteAcc, NoLock, Preserve)
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{
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G1S, 8, //SWC GPE1_STS
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Offset(0x4),
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G1E, 8,
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Offset(0xA),
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G1S2, 8, //SWC GPE1_STS_2
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G1S3, 8 //SWC GPE1_STS_3
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}
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OperationRegion (SWC1, SystemIO, \PMBS, 0x2C)
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Field(SWC1, DWordAcc, NoLock, Preserve)
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{
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Offset(0x20),
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G0S, 32, //GPE0_STS
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Offset(0x28),
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G0EN, 32 //GPE0_EN
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}
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// Prepare to Sleep. The hook is called when the OS is about to
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// enter a sleep state. The argument passed is the numeric value of
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// the Sx state.
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Method(_PTS,1)
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{
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Store(0,P80D) // Zero out the entire Port 80h DWord.
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P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0.
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//clear the 3 SWC status bits
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Store(Ones, G1S3)
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Store(Ones, G1S2)
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Store(1, G1S)
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//set SWC GPE1_EN
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Store(1,G1E)
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//clear GPE0_STS
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Store(Ones, G0S)
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If(LEqual(Arg0,3)) // If S3 Suspend
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{
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//
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// Disable Digital Thermal Sensor function when doing S3 suspend
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//
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If(CondRefOf(DTSE))
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{
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If(LGreaterEqual(DTSE, 0x01))
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{
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Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI
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Store(0xD0, SSMP) // DTS SW SMI
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}
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}
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}
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}
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// Wake. This hook is called when the OS is about to wake from a
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// sleep state. The argument passed is the numeric value of the
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// sleep state the system is waking from.
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Method(_WAK,1,Serialized)
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{
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P8XH(1,0xAB) // Beginning of _WAK.
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Notify(\_SB.PWRB,0x02)
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If(NEXP)
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{
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// Reinitialize the Native PCI Express after resume
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If(And(OSCC,0x02))
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{
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\_SB.PCI0.NHPG()
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}
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If(And(OSCC,0x04)) // PME control granted?
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{
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\_SB.PCI0.NPME()
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}
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}
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If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume
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{
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// If CMP is enabled, we may need to restore the C-State and/or
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// P-State configuration, as it may have been saved before the
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// configuration was finalized based on OS/driver support.
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//
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// CFGD[24] = Two or more cores enabled
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//
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If(And(CFGD,0x01000000))
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{
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//
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// If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if
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// C-States are enabled.
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//
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// CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled
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//
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//
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}
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// Windows XP SP2 does not properly restore the P-State
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// upon resume from S4 or S3 with degrade modes enabled.
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// Use the existing _PPC methods to cycle the available
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// P-States such that the processor ends up running at
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// the proper P-State.
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//
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// Note: For S4, another possible W/A is to always boot
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// the system in LFM.
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//
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If(LEqual(OSYS,2002))
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{
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If(And(CFGD,0x01))
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{
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If(LGreater(\_PR.CPU0._PPC,0))
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{
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Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
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PNOT()
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Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
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PNOT()
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}
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Else
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{
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Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
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PNOT()
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Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)
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PNOT()
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}
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}
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}
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}
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Return(Package() {0,0})
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}
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// Power Notification:
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// Perform all needed OS notifications during a
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// Power Switch.
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//
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// Arguments:
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// None
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//
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// Return Value:
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// None
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Method(PNOT,0,Serialized)
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{
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// If MP enabled and driver support is present, notify all
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// processors.
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If(MPEN)
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{
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If(And(PDC0,0x0008))
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{
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Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC.
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If(And(PDC0,0x0010))
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{
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Sleep(100)
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Notify(\_PR.CPU0,0x81) // Eval _CST.
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}
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}
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If(And(PDC1,0x0008))
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{
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Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC.
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If(And(PDC1,0x0010))
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{
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Sleep(100)
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Notify(\_PR.CPU1,0x81) // Eval _CST.
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}
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}
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If(And(PDC2,0x0008))
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{
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Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC.
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If(And(PDC2,0x0010))
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{
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Sleep(100)
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Notify(\_PR.CPU2,0x81) // Eval _CST.
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}
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}
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If(And(PDC3,0x0008))
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{
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Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC.
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If(And(PDC3,0x0010))
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{
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Sleep(100)
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Notify(\_PR.CPU3,0x81) // Eval _CST.
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}
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}
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}
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Else
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{
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Notify(\_PR.CPU0,0x80) // Eval _PPC.
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Sleep(100)
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Notify(\_PR.CPU0,0x81) // Eval _CST
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}
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}
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//
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// System Bus
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//
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Scope(\_SB)
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{
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Name(CRTT, 110) // Processor critical temperature
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Name(ACTT, 77) // Active temperature limit for processor participant
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Name(GCR0, 70) // Critical temperature for Generic participant 0 in degree celsius
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Name(GCR1, 70) // Critical temperature for Generic participant 1 in degree celsius
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Name(GCR2, 70) // Critical temperature for Generic participant 2 in degree celsius
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Name(GCR3, 70) // Critical temperature for Generic participant 3 in degree celsius
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Name(GCR4, 70) // Critical temperature for Generic participant 4 in degree celsius
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Name(GCR5, 70) // Critical temperature for Generic participant 5 in degree celsius
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Name(GCR6, 70) // Critical temperature for Generic participant 6 in degree celsius
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Name(PST0, 60) // Passive temperature limit for Generic Participant 0 in degree celsius
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Name(PST1, 60) // Passive temperature limit for Generic Participant 1 in degree celsius
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Name(PST2, 60) // Passive temperature limit for Generic Participant 2 in degree celsius
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Name(PST3, 60) // Passive temperature limit for Generic Participant 3 in degree celsius
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Name(PST4, 60) // Passive temperature limit for Generic Participant 4 in degree celsius
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Name(PST5, 60) // Passive temperature limit for Generic Participant 5 in degree celsius
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Name(PST6, 60) // Passive temperature limit for Generic Participant 6 in degree celsius
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Name(LPMV, 3)
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Name(PDBG, 0) // DPTF Super debug option
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Name(PDPM, 1) // DPTF DPPM enable
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Name(PDBP, 1) // DPTF DBPT enable (dynamic battery protection technology)
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Name(DLPO, Package()
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{
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0x1, // Revision
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0x1, // LPO Enable
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0x1, // LPO StartPState
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25, // LPO StepSize
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0x1, //
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0x1, //
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})
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Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change
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// or it is from Graphics driver. Value of 1 is for DPTF else it is 0
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Method(_INI,0)
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{
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// NVS has stale DTS data. Get and update the values
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// with current temperatures. Note that this will also
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// re-arm any AP Thermal Interrupts.
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// Read temperature settings from global NVS
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Store(DPCT, CRTT)
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Store(Subtract(DPPT, 8), ACTT) // Active Trip point = Passive trip point - 8
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Store(DGC0, GCR0)
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Store(DGC0, GCR1)
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Store(DGC1, GCR2)
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Store(DGC1, GCR3)
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Store(DGC1, GCR4)
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Store(DGC2, GCR5)
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Store(DGC2, GCR6)
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Store(DGP0, PST0)
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Store(DGP0, PST1)
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Store(DGP1, PST2)
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Store(DGP1, PST3)
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Store(DGP1, PST4)
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Store(DGP2, PST5)
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Store(DGP2, PST6)
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// Read Current low power mode setting from global NVS
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Store(DLPM, LPMV)
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// Update DPTF Super Debug option
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Store(DDBG, PDBG)
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// Update DPTF LPO Options
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Store(LPOE, Index(DLPO,1))
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Store(LPPS, Index(DLPO,2))
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Store(LPST, Index(DLPO,3))
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Store(LPPC, Index(DLPO,4))
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Store(LPPF, Index(DLPO,5))
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Store(DPME, PDPM)
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}
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// Define a (Control Method) Power Button.
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Device(PWRB)
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{
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Name(_HID,EISAID("PNP0C0C"))
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// GPI_SUS0 = GPE16 = Waketime SCI. The PRW isn't working when
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// placed in any of the logical locations ( PS2K, PS2M),
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// so a Power Button Device was created specifically
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// for the WAKETIME_SCI PRW.
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Name(_PRW, Package() {16,4})
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}
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Device(SLPB)
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{
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Name(_HID, EISAID("PNP0C0E"))
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} // END SLPB
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Scope(PCI0)
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{
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Method(_INI,0)
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{
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// Determine the OS and store the value, where:
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//
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// OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
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// OSYS = 2012 = Windows 8 and Windows Server 2012.
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//
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// Assume Windows 7 at a minimum.
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Store(2009,OSYS)
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// Check for a specific OS which supports _OSI.
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If(CondRefOf(\_OSI,Local0))
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{
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// Linux returns _OSI = TRUE for numerous Windows
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// strings so that it is fully compatible with
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// BIOSes available in the market today. There are
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// currently 2 known exceptions to this model:
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// 1) Video Repost - Linux supports S3 without
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// requireing a Driver, meaning a Video
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// Repost will be required.
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// 2) On-Screen Branding - a full CMT Logo
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// is limited to the WIN2K and WINXP
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// Operating Systems only.
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// Use OSYS for Windows Compatibility.
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If(\_OSI("Windows 2009")) // Windows 7 or Windows Server 2008 R2
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{
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Store(2009,OSYS)
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}
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If(\_OSI("Windows 2012")) // Windows 8 or Windows Server 2012
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{
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Store(2012,OSYS)
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}
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If(\_OSI("Windows 2013")) //Windows Blue
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{
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Store(2013,OSYS)
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}
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//
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// If CMP is enabled, enable SMM C-State
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// coordination. SMM C-State coordination
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// will be disabled in _PDC if driver support
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// for independent C-States deeper than C1
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// is indicated.
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}
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}
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Method(NHPG,0,Serialized)
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{
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}
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Method(NPME,0,Serialized)
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{
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}
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} // end Scope(PCI0)
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Device (GPED) //virtual GPIO device for ASL based AC/Battery/Expection notification
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{
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Name (_ADR, 0)
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Name (_HID, "INT0002")
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Name (_CID, "INT0002")
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Name (_DDN, "Virtual GPIO controller" )
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Name (_UID, 1)
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Method (_CRS, 0x0, Serialized)
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{
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Name (RBUF, ResourceTemplate ()
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{
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Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9
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})
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Return (RBUF)
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0x0)
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}
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Method (_AEI, 0x0, Serialized)
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{
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Name(RBUF, ResourceTemplate()
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{
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GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2
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})
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Return(RBUF)
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}
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Method(_E02) // _Exx method will be called when interrupt is raised
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{
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If (LEqual (PWBS, 1))
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{
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Store (1, PWBS) //Clear PowerButton Status
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}
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If (LEqual (PMEB, 1))
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{
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Store (1, PMEB) //Clear PME_B0_STS
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}
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If (LEqual (\_SB.PCI0.SATA.PMES, 1))
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{
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Store (1, \_SB.PCI0.SATA.PMES)
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Notify (\_SB.PCI0.SATA, 0x02)
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}
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//
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// eMMC 4.41
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//
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If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1)))
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{
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Store (1, \_SB.PCI0.EM41.PMES)
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Notify (\_SB.PCI0.EM41, 0x02)
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}
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//
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// eMMC 4.5
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//
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If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1)))
|
|
{
|
|
Store (1, \_SB.PCI0.EM45.PMES)
|
|
Notify (\_SB.PCI0.EM45, 0x02)
|
|
}
|
|
|
|
If (LEqual(HDAD, 0))
|
|
{
|
|
If (LEqual (\_SB.PCI0.HDEF.PMES, 1))
|
|
{
|
|
Store (1, \_SB.PCI0.HDEF.PMES)
|
|
Notify (\_SB.PCI0.HDEF, 0x02)
|
|
}
|
|
}
|
|
|
|
If (LEqual (\_SB.PCI0.EHC1.PMES, 1))
|
|
{
|
|
Store (1, \_SB.PCI0.EHC1.PMES)
|
|
Notify (\_SB.PCI0.EHC1, 0x02)
|
|
}
|
|
If (LEqual (\_SB.PCI0.XHC1.PMES, 1))
|
|
{
|
|
Store (1, \_SB.PCI0.XHC1.PMES)
|
|
Notify (\_SB.PCI0.XHC1, 0x02)
|
|
}
|
|
If (LEqual (\_SB.PCI0.SEC0.PMES, 1))
|
|
{
|
|
Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES)
|
|
Notify (\_SB.PCI0.SEC0, 0x02)
|
|
}
|
|
}
|
|
} // Device (GPED)
|
|
|
|
//--------------------
|
|
// GPIO
|
|
//--------------------
|
|
Device (GPO0)
|
|
{
|
|
Name (_ADR, 0)
|
|
Name (_HID, "INT33FC")
|
|
Name (_CID, "INT33B2")
|
|
Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" )
|
|
Name (_UID, 1)
|
|
Method (_CRS, 0x0, Serialized)
|
|
{
|
|
Name (RBUF, ResourceTemplate ()
|
|
{
|
|
Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000)
|
|
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49}
|
|
|
|
})
|
|
Return (RBUF)
|
|
}
|
|
|
|
Method (_STA, 0x0, NotSerialized)
|
|
{
|
|
//
|
|
// GPO driver will report present if any of below New IO bus exist
|
|
//
|
|
If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist
|
|
{ Return(0xF) }
|
|
If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist
|
|
{ Return(0xF) }
|
|
If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist
|
|
{ Return(0xF) }
|
|
If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist
|
|
{ Return(0xF) }
|
|
If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist
|
|
{ Return(0xF) }
|
|
If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist
|
|
{ Return(0xF) }
|
|
If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist
|
|
{ Return(0xF) }
|
|
If (LEqual(L27D, 0)) // LPIO2 I2C #7 exist
|
|
{ Return(0xF) }
|
|
|
|
Return(0x0)
|
|
}
|
|
|
|
// Track status of GPIO OpRegion availability for this controller
|
|
Name(AVBL, 0)
|
|
Method(_REG,2)
|
|
{
|
|
If (Lequal(Arg0, 8))
|
|
{
|
|
Store(Arg1, ^AVBL)
|
|
}
|
|
}
|
|
|
|
OperationRegion(GPOP, SystemIo, \GPBS, 0x50)
|
|
Field(GPOP, ByteAcc, NoLock, Preserve) {
|
|
Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h
|
|
, 21,
|
|
BTD3, 1, //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP
|
|
Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h
|
|
, 30,
|
|
SHD3, 1 //GPIO_S0_SC_95 - SENS_HUB_RST_N
|
|
}
|
|
|
|
|
|
|
|
} // Device (GPO0)
|
|
|
|
Device (GPO1)
|
|
{
|
|
Name (_ADR, 0)
|
|
Name (_HID, "INT33FC")
|
|
Name (_CID, "INT33B2")
|
|
Name (_DDN, "ValleyView2 GPNCORE controller" )
|
|
Name (_UID, 2)
|
|
Method (_CRS, 0x0, Serialized)
|
|
{
|
|
Name (RBUF, ResourceTemplate ()
|
|
{
|
|
Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000)
|
|
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48}
|
|
})
|
|
Return (RBUF)
|
|
}
|
|
|
|
Method (_STA, 0x0, NotSerialized)
|
|
{
|
|
Return(\_SB.GPO0._STA)
|
|
}
|
|
} // Device (GPO1)
|
|
|
|
Device (GPO2)
|
|
{
|
|
Name (_ADR, 0)
|
|
Name (_HID, "INT33FC")
|
|
Name (_CID, "INT33B2")
|
|
Name (_DDN, "ValleyView2 GPSUS controller" )
|
|
Name (_UID, 3)
|
|
Method (_CRS, 0x0, Serialized)
|
|
{
|
|
Name (RBUF, ResourceTemplate ()
|
|
{
|
|
Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000)
|
|
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50}
|
|
})
|
|
Return (RBUF)
|
|
}
|
|
|
|
Method (_STA, 0x0, NotSerialized)
|
|
{
|
|
Return(^^GPO0._STA)
|
|
}
|
|
|
|
// Track status of GPIO OpRegion availability for this controller
|
|
Name(AVBL, 0)
|
|
Method(_REG,2)
|
|
{
|
|
If (Lequal(Arg0, 8))
|
|
{
|
|
Store(Arg1, ^AVBL)
|
|
}
|
|
}
|
|
//Manipulate GPIO line using GPIO operation regions.
|
|
Name (GMOD, ResourceTemplate () //One method of creating a Connection for OpRegion accesses in Field definitions
|
|
{
|
|
//is creating a named object that refers to the connection attributes
|
|
GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21} //sus 21+128 BT+WLAN_ENABLE
|
|
})
|
|
|
|
OperationRegion(GPOP, SystemIo, \GPBS, 0x100)
|
|
Field(GPOP, ByteAcc, NoLock, Preserve) {
|
|
Offset(0x88), // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h
|
|
, 20,
|
|
WFD3, 1
|
|
}
|
|
|
|
|
|
} // Device (GPO2)
|
|
include ("PchScc.asl")
|
|
include ("PchLpss.asl")
|
|
|
|
Scope(I2C7)
|
|
{
|
|
|
|
} //End Scope(I2C7)
|
|
|
|
} // end Scope(\_SB)
|
|
|
|
Name(PICM, 0) // Global Name, returns current Interrupt controller mode; updated from _PIC control method
|
|
|