91a03f78ba
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspWrapperPlatformSecLibSample support for X64. 2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample. 3.Moved Fsp.h up one level to be shared across IA32 and X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
150 lines
2.8 KiB
NASM
150 lines
2.8 KiB
NASM
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; PeiCoreEntry.nasm
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;
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; Abstract:
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;
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; Find and call SecStartup
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;
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;------------------------------------------------------------------------------
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SECTION .text
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%include "PushPopRegsNasm.inc"
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extern ASM_PFX(SecStartup)
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extern ASM_PFX(PlatformInit)
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;
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; args 1:XMM, 2:REG, 3:IDX
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;
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%macro LXMMN 3
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pextrq %2, %1, (%3 & 3)
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%endmacro
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;
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; args 1:YMM, 2:XMM, 3:IDX (0 - lower 128bits, 1 - upper 128bits)
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;
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%macro LYMMN 3
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vextractf128 %2, %1, %3
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%endmacro
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%macro LOAD_TS 1
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LYMMN ymm6, xmm5, 1
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LXMMN xmm5, %1, 1
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%endmacro
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global ASM_PFX(CallPeiCoreEntryPoint)
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ASM_PFX(CallPeiCoreEntryPoint):
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;
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; Per X64 calling convention, make sure RSP is 16-byte aligned.
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;
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mov rax, rsp
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and rax, 0fh
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sub rsp, rax
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;
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; Platform init
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;
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PUSHA_64
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sub rsp, 20h
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call ASM_PFX(PlatformInit)
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add rsp, 20h
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POPA_64
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;
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; Set stack top pointer
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;
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mov rsp, r8
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;
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; Push the hob list pointer
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;
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push rcx
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;
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; RBP holds start of BFV passed from Vtf0. Save it to r10.
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;
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mov r10, rbp
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;
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; Save the value
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; RDX: start of range
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; r8: end of range
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;
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mov rbp, rsp
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push rdx
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push r8
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mov r14, rdx
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mov r15, r8
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;
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; Push processor count to stack first, then BIST status (AP then BSP)
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;
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mov eax, 1
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cpuid
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shr ebx, 16
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and ebx, 0000000FFh
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cmp bl, 1
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jae PushProcessorCount
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;
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; Some processors report 0 logical processors. Effectively 0 = 1.
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; So we fix up the processor count
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;
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inc ebx
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PushProcessorCount:
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sub rsp, 4
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mov rdi, rsp
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mov DWORD [rdi], ebx
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;
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; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
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; for all processor threads
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;
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xor ecx, ecx
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mov cl, bl
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PushBist:
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sub rsp, 4
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mov rdi, rsp
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movd eax, mm0
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mov DWORD [rdi], eax
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loop PushBist
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; Save Time-Stamp Counter
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LOAD_TS rax
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push rax
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;
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; Pass entry point of the PEI core
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;
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mov rdi, 0FFFFFFE0h
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mov edi, DWORD [rdi]
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mov r9, rdi
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;
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; Pass BFV into the PEI Core
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;
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mov r8, r10
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;
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; Pass stack size into the PEI Core
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;
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mov rcx, r15 ; Start of TempRam
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mov rdx, r14 ; End of TempRam
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sub rcx, rdx ; Size of TempRam
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;
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; Pass Control into the PEI Core
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;
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sub rsp, 20h
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call ASM_PFX(SecStartup)
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