429309e0c6
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
97 lines
2.5 KiB
C
97 lines
2.5 KiB
C
/** @file
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Functions for ARM processor information
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Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <IndustryStandard/ArmCache.h>
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#include <Library/ArmLib.h>
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#include "SmbiosProcessor.h"
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/** Gets the size of the specified cache.
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@param CacheLevel The cache level (L1, L2 etc.).
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@param DataCache Whether the cache is a dedicated data cache.
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@param UnifiedCache Whether the cache is a unified cache.
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@return The cache size.
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**/
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UINT64
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SmbiosProcessorGetCacheSize (
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IN UINT8 CacheLevel,
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IN BOOLEAN DataCache,
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IN BOOLEAN UnifiedCache
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)
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{
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CCSIDR_DATA Ccsidr;
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CCSIDR2_DATA Ccsidr2;
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CSSELR_DATA Csselr;
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BOOLEAN CcidxSupported;
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UINT64 CacheSize;
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// Read the CCSIDR register to get the cache architecture
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Csselr.Data = 0;
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Csselr.Bits.Level = CacheLevel - 1;
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Csselr.Bits.InD = (!DataCache && !UnifiedCache);
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Ccsidr.Data = ReadCCSIDR (Csselr.Data);
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CcidxSupported = ArmHasCcidx ();
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if (CcidxSupported) {
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Ccsidr2.Data = ReadCCSIDR2 (Csselr.Data);
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CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *
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(Ccsidr.BitsCcidxAA32.Associativity + 1) *
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(Ccsidr2.Bits.NumSets + 1);
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} else {
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CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *
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(Ccsidr.BitsNonCcidx.Associativity + 1) *
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(Ccsidr.BitsNonCcidx.NumSets + 1);
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}
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return CacheSize;
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}
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/** Gets the associativity of the specified cache.
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@param CacheLevel The cache level (L1, L2 etc.).
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@param DataCache Whether the cache is a dedicated data cache.
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@param UnifiedCache Whether the cache is a unified cache.
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@return The cache associativity.
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**/
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UINT32
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SmbiosProcessorGetCacheAssociativity (
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IN UINT8 CacheLevel,
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IN BOOLEAN DataCache,
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IN BOOLEAN UnifiedCache
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)
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{
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CCSIDR_DATA Ccsidr;
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CSSELR_DATA Csselr;
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BOOLEAN CcidxSupported;
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UINT32 Associativity;
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// Read the CCSIDR register to get the cache architecture
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Csselr.Data = 0;
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Csselr.Bits.Level = CacheLevel - 1;
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Csselr.Bits.InD = (!DataCache && !UnifiedCache);
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Ccsidr.Data = ReadCCSIDR (Csselr.Data);
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CcidxSupported = ArmHasCcidx ();
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if (CcidxSupported) {
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Associativity = Ccsidr.BitsCcidxAA32.Associativity + 1;
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} else {
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Associativity = Ccsidr.BitsNonCcidx.Associativity + 1;
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}
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return Associativity;
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}
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