2eff4ddc77
To substantially reduce the amount of processing that takes place with the MMU and caches off, implement a version of ArmPlatformLib specific for QEMU/mach-virt in AArch64 mode that carries a statically allocated and populated ID map that covers the NOR flash and device region, and 128 MiB of DRAM at the base of memory (0x4000_0000). Note that 128 MiB has always been the minimum amount of DRAM we support for this configuration, and the existing code already ASSERT()s in DEBUG mode when booting with less. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
58 lines
1.8 KiB
ArmAsm
58 lines
1.8 KiB
ArmAsm
// SPDX-License-Identifier: BSD-2-Clause-Patent
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// Copyright 2022 Google LLC
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// Author: Ard Biesheuvel <ardb@google.com>
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.set TT_TYPE_BLOCK, 0x1
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.set TT_TYPE_PAGE, 0x3
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.set TT_TYPE_TABLE, 0x3
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.set TT_AF, 0x1 << 10
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.set TT_NG, 0x1 << 11
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.set TT_RO, 0x2 << 6
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.set TT_XN, 0x3 << 53
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.set TT_MT_DEV, 0x0 << 2 // MAIR #0
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.set TT_MT_MEM, (0x3 << 2) | (0x3 << 8) // MAIR #3
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.set PAGE_XIP, TT_TYPE_PAGE | TT_MT_MEM | TT_AF | TT_RO | TT_NG
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.set BLOCK_DEV, TT_TYPE_BLOCK | TT_MT_DEV | TT_AF | TT_XN | TT_NG
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.set BLOCK_MEM, TT_TYPE_BLOCK | TT_MT_MEM | TT_AF | TT_XN | TT_NG
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.globl idmap
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.section ".rodata.idmap", "a", %progbits
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.align 12
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idmap: /* level 0 */
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.quad 1f + TT_TYPE_TABLE
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.fill 511, 8, 0x0
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1: /* level 1 */
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.quad 20f + TT_TYPE_TABLE // 1 GB of flash and device mappings
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.quad 21f + TT_TYPE_TABLE // up to 1 GB of DRAM
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.fill 510, 8, 0x0 // 510 GB of remaining VA space
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20: /* level 2 */
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.quad 3f + TT_TYPE_TABLE // up to 2 MB of flash
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.fill 63, 8, 0x0 // 126 MB of unused flash
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.set idx, 64
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.rept 448
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.quad BLOCK_DEV | (idx << 21) // 896 MB of RW- device mappings
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.set idx, idx + 1
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.endr
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21: /* level 2 */
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.set idx, 0x40000000 >> 21
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.rept 64
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.quad BLOCK_MEM | (idx << 21) // 128 MB of RW- memory mappings
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.set idx, idx + 1
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.endr
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.fill 448, 8, 0x0
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3: /* level 3 */
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.quad 0x0 // omit first 4k page
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.set idx, 1
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.rept 511
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.quad PAGE_XIP | (idx << 12) // 2044 KiB of R-X flash mappings
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.set idx, idx + 1
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.endr
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