e6042aec1b
While RISC-V hart is trapped into S-Mode, the S-Mode interrupt CSR (SIE) is disabled by RISC-V hart. However the (SIE) is enabled again by RestoreTPL, this causes the second S-Mode trap is triggered by the machine mode (M-Mode)timer interrupt redirection. The SRET instruction clear Supervisor Previous Privilege (SPP) to zero (User mode) in the second S-Mode interrupt according to the RISC-V spec. Above brings hart to the user mode (U-Mode) when execute SRET in the nested S-Mode interrupt handler because SPP is set to User Mode in the second interrupt. Afterward, system runs in U-Mode and any accesses to S-Mode CSR causes the invalid instruction exception. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <liming.gao@intel.com>
64 lines
1.9 KiB
ArmAsm
64 lines
1.9 KiB
ArmAsm
//------------------------------------------------------------------------------
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//
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// RISC-V Supervisor Mode interrupt enable/disable
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
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ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
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ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
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#define SSTATUS_SIE 0x00000002
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#define CSR_SSTATUS 0x100
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#define SSTATUS_SPP_BIT_POSITION 8
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//
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// This routine disables supervisor mode interrupt
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//
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ASM_PFX(RiscVDisableSupervisorModeInterrupts):
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add sp, sp, -(__SIZEOF_POINTER__)
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sd a1, (sp)
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li a1, SSTATUS_SIE
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csrc CSR_SSTATUS, a1
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ld a1, (sp)
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add sp, sp, (__SIZEOF_POINTER__)
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ret
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//
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// This routine enables supervisor mode interrupt
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//
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ASM_PFX(RiscVEnableSupervisorModeInterrupt):
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add sp, sp, -2*(__SIZEOF_POINTER__)
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sd a0, (0*__SIZEOF_POINTER__)(sp)
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sd a1, (1*__SIZEOF_POINTER__)(sp)
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csrr a0, CSR_SSTATUS
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and a0, a0, (1 << SSTATUS_SPP_BIT_POSITION)
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bnez a0, InTrap // We are in supervisor mode (SMode)
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// trap handler.
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// Skip enabling SIE becasue SIE
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// is set to disabled by RISC-V hart
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// when the trap takes hart to SMode.
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li a1, SSTATUS_SIE
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csrs CSR_SSTATUS, a1
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InTrap:
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ld a0, (0*__SIZEOF_POINTER__)(sp)
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ld a1, (1*__SIZEOF_POINTER__)(sp)
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add sp, sp, 2*(__SIZEOF_POINTER__)
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ret
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//
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// This routine returns supervisor mode interrupt
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// status.
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//
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ASM_PFX(RiscVGetSupervisorModeInterrupts):
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csrr a0, CSR_SSTATUS
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andi a0, a0, SSTATUS_SIE
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ret
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