d3febfd9ad
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
48 lines
1.2 KiB
NASM
48 lines
1.2 KiB
NASM
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; SetMem32.nasm
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;
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; Abstract:
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;
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; SetMem32 function
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; VOID *
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; InternalMemSetMem32 (
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; IN VOID *Buffer,
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; IN UINTN Count,
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; IN UINT32 Value
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; )
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;------------------------------------------------------------------------------
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global ASM_PFX(InternalMemSetMem32)
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ASM_PFX(InternalMemSetMem32):
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movq mm0, r8
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mov rax, rcx ; rax <- Buffer
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xchg rcx, rdx ; rcx <- Count rdx <- Buffer
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shr rcx, 1 ; rcx <- # of qwords to set
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jz @SetDwords
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pshufw mm0, mm0, 44h
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.0:
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movntq [rdx], mm0
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lea rdx, [rdx + 8] ; use "lea" to avoid flag changes
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loop .0
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mfence
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@SetDwords:
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jnc .1
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movd [rdx], mm0
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.1:
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ret
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