60d8bb9f28
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte via Linear- Address Translation to a 1-GByte Page. Build Tool: if the nasm is not found it will throw Build errors like FileNotFoundError: [WinError 2]The system cannot find the file specified run the command wil try except block to get meaningful error message Test Result: Tested in both Simulation environment and Hardware both works fine without any issues. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Sahil Dureja <sahil.dureja@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
54 lines
1.5 KiB
NASM
54 lines
1.5 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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; Linear-Address Translation to a 1-GByte Page
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;
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;------------------------------------------------------------------------------
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BITS 64
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%define ALIGN_TOP_TO_4K_FOR_PAGING
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%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_DIRTY + \
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PAGE_PRESENT + \
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PAGE_SIZE)
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%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
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%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
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%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
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PAGE_PDP_ATTR)
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%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
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ALIGN 16
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TopLevelPageDirectory:
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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DQ PDP(0x1000)
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TIMES 0x1000-PGTBLS_OFFSET($) DB 0
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;
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; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
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;
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%assign i 0
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%rep 512
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DQ PDP_1G(i)
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%assign i i+1
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%endrep
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TIMES 0x2000-PGTBLS_OFFSET($) DB 0
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EndOfPageTables:
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