0d4c1db81a
The PiSmmCpuDxeSmm module makes some assumptions about GDT selectors that are based on the GDT layout from the DxeIplPeim. For example, the protected mode entry code and (where appropriate) the long mode entry code in the UefiCpuPkg/PiSmmCpuDxeSmm/*/MpFuncs.* assembly files, which are used during S3 resume, open-code segment selector values that depend on DxeIplPeim's GDT layout. This updates the CpuDxe module to use the same GDT layout as the DxeIplPeim. This enables modules that are dispatched after CpuDxe to find, and potentially save and restore, a GDT layout that matches that of DxeIplPeim. The DxeIplPeim has a 2 GDT entries for data selectors that are identical. These are LINEAR_SEL (GDT Offset 0x08)and LINEAR_DATA64_SEL (GDT offset 0x30). LINEAL_SEL is used for for IA32 DXE and the LINEAR_DATA64_SEL is used for X64 DXE. This duplicate data selector was added to the CpuDxe module to keep the GDT and all selectors consistent. Using a consistent GDT also improves debug experience. Reported-by: Laszlo Ersek <lersek@redhat.com> Analyzed-by: Laszlo Ersek <lersek@redhat.com> Link: http://article.gmane.org/gmane.comp.bios.edk2.devel/3568 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18710 6f19259b-4bc3-4df7-8a09-765794883524
162 lines
3.8 KiB
C
162 lines
3.8 KiB
C
/** @file
|
|
C based implemention of IA32 interrupt handling only
|
|
requiring a minimal assembly interrupt entry point.
|
|
|
|
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
|
|
This program and the accompanying materials
|
|
are licensed and made available under the terms and conditions of the BSD License
|
|
which accompanies this distribution. The full text of the license may be found at
|
|
http://opensource.org/licenses/bsd-license.php
|
|
|
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
|
|
**/
|
|
|
|
#include "CpuDxe.h"
|
|
#include "CpuGdt.h"
|
|
|
|
//
|
|
// Global descriptor table (GDT) Template
|
|
//
|
|
STATIC GDT_ENTRIES GdtTemplate = {
|
|
//
|
|
// NULL_SEL
|
|
//
|
|
{
|
|
0x0, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x0, // type
|
|
0x0, // limit 19:16, flags
|
|
0x0, // base 31:24
|
|
},
|
|
//
|
|
// LINEAR_SEL
|
|
//
|
|
{
|
|
0x0FFFF, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x092, // present, ring 0, data, read/write
|
|
0x0CF, // page-granular, 32-bit
|
|
0x0,
|
|
},
|
|
//
|
|
// LINEAR_CODE_SEL
|
|
//
|
|
{
|
|
0x0FFFF, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x09F, // present, ring 0, code, execute/read, conforming, accessed
|
|
0x0CF, // page-granular, 32-bit
|
|
0x0,
|
|
},
|
|
//
|
|
// SYS_DATA_SEL
|
|
//
|
|
{
|
|
0x0FFFF, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x093, // present, ring 0, data, read/write, accessed
|
|
0x0CF, // page-granular, 32-bit
|
|
0x0,
|
|
},
|
|
//
|
|
// SYS_CODE_SEL
|
|
//
|
|
{
|
|
0x0FFFF, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x09A, // present, ring 0, code, execute/read
|
|
0x0CF, // page-granular, 32-bit
|
|
0x0,
|
|
},
|
|
//
|
|
// SPARE4_SEL
|
|
//
|
|
{
|
|
0x0, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x0, // type
|
|
0x0, // limit 19:16, flags
|
|
0x0, // base 31:24
|
|
},
|
|
//
|
|
// LINEAR_DATA64_SEL
|
|
//
|
|
{
|
|
0x0FFFF, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x092, // present, ring 0, data, read/write
|
|
0x0CF, // page-granular, 32-bit
|
|
0x0,
|
|
},
|
|
//
|
|
// LINEAR_CODE64_SEL
|
|
//
|
|
{
|
|
0x0FFFF, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x09A, // present, ring 0, code, execute/read
|
|
0x0AF, // page-granular, 64-bit code
|
|
0x0, // base (high)
|
|
},
|
|
//
|
|
// SPARE5_SEL
|
|
//
|
|
{
|
|
0x0, // limit 15:0
|
|
0x0, // base 15:0
|
|
0x0, // base 23:16
|
|
0x0, // type
|
|
0x0, // limit 19:16, flags
|
|
0x0, // base 31:24
|
|
},
|
|
};
|
|
|
|
/**
|
|
Initialize Global Descriptor Table.
|
|
|
|
**/
|
|
VOID
|
|
InitGlobalDescriptorTable (
|
|
VOID
|
|
)
|
|
{
|
|
GDT_ENTRIES *gdt;
|
|
IA32_DESCRIPTOR gdtPtr;
|
|
|
|
//
|
|
// Allocate Runtime Data for the GDT
|
|
//
|
|
gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
|
|
ASSERT (gdt != NULL);
|
|
gdt = ALIGN_POINTER (gdt, 8);
|
|
|
|
//
|
|
// Initialize all GDT entries
|
|
//
|
|
CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));
|
|
|
|
//
|
|
// Write GDT register
|
|
//
|
|
gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
|
|
gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);
|
|
AsmWriteGdtr (&gdtPtr);
|
|
|
|
//
|
|
// Update selector (segment) registers base on new GDT
|
|
//
|
|
SetCodeSelector ((UINT16)CPU_CODE_SEL);
|
|
SetDataSelectors ((UINT16)CPU_DATA_SEL);
|
|
}
|
|
|