7947da3ccc
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18646 6f19259b-4bc3-4df7-8a09-765794883524
133 lines
3.7 KiB
C
133 lines
3.7 KiB
C
/** @file
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Page table manipulation functions for IA-32 processors
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Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PiSmmCpuDxeSmm.h"
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SPIN_LOCK mPFLock;
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/**
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Create PageTable for SMM use.
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@return PageTable Address
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**/
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UINT32
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SmmInitPageTable (
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VOID
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)
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{
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UINTN PageFaultHandlerHookAddress;
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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//
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// Initialize spin lock
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//
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InitializeSpinLock (&mPFLock);
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if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
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//
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// Set own Page Fault entry instead of the default one, because SMM Profile
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// feature depends on IRET instruction to do Single Step
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//
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PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;
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IdtEntry += EXCEPT_IA32_PAGE_FAULT;
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IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
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IdtEntry->Bits.Reserved_0 = 0;
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IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
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} else {
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//
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// Register SMM Page Fault Handler
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//
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SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_PAGE_FAULT, SmiPFHandler);
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}
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//
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// Additional SMM IDT initialization for SMM stack guard
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//
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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InitializeIDTSmmStackGuard ();
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}
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return Gen4GPageTable (0);
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}
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/**
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Page Fault handler for SMM use.
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**/
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VOID
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SmiDefaultPFHandler (
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VOID
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)
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{
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CpuDeadLoop ();
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}
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/**
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ThePage Fault handler wrapper for SMM use.
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@param InterruptType Defines the type of interrupt or exception that
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occurred on the processor.This parameter is processor architecture specific.
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@param SystemContext A pointer to the processor context when
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the interrupt occurred on the processor.
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**/
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VOID
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EFIAPI
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SmiPFHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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UINTN PFAddress;
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ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);
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AcquireSpinLock (&mPFLock);
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PFAddress = AsmReadCr2 ();
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if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
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(PFAddress >= mCpuHotPlugData.SmrrBase) &&
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(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
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DEBUG ((EFI_D_ERROR, "SMM stack overflow!\n"));
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CpuDeadLoop ();
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}
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//
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// If a page fault occurs in SMM range
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//
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if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
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(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
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if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
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DEBUG ((EFI_D_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));
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DEBUG_CODE (
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DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);
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);
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CpuDeadLoop ();
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}
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}
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if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
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SmmProfilePFHandler (
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SystemContext.SystemContextIa32->Eip,
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SystemContext.SystemContextIa32->ExceptionData
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);
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} else {
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SmiDefaultPFHandler ();
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}
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ReleaseSpinLock (&mPFLock);
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}
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