84338c0d49
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790 Replace Opcode with the corresponding instructions. The code changes have been verified with CompareBuild.py tool, which can be used to compare the results of two different EDK II builds to determine if they generate the same binaries. (tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild) Signed-off-by: Jason Lou <yun.lou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
567 lines
20 KiB
NASM
567 lines
20 KiB
NASM
;/** @file
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; Low level x64 routines used by the debug support driver.
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;
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; Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;**/
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%define EXCPT64_DIVIDE_ERROR 0
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%define EXCPT64_DEBUG 1
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%define EXCPT64_NMI 2
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%define EXCPT64_BREAKPOINT 3
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%define EXCPT64_OVERFLOW 4
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%define EXCPT64_BOUND 5
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%define EXCPT64_INVALID_OPCODE 6
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%define EXCPT64_DOUBLE_FAULT 8
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%define EXCPT64_INVALID_TSS 10
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%define EXCPT64_SEG_NOT_PRESENT 11
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%define EXCPT64_STACK_FAULT 12
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%define EXCPT64_GP_FAULT 13
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%define EXCPT64_PAGE_FAULT 14
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%define EXCPT64_FP_ERROR 16
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%define EXCPT64_ALIGNMENT_CHECK 17
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%define EXCPT64_MACHINE_CHECK 18
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%define EXCPT64_SIMD 19
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%define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags
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SECTION .data
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global ASM_PFX(OrigVector)
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global ASM_PFX(InterruptEntryStub)
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global ASM_PFX(StubSize)
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global ASM_PFX(CommonIdtEntry)
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global ASM_PFX(FxStorSupport)
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extern ASM_PFX(InterruptDistrubutionHub)
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ASM_PFX(StubSize): dd InterruptEntryStubEnd - ASM_PFX(InterruptEntryStub)
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AppRsp: dq 0x1111111111111111 ; ?
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DebugRsp: dq 0x2222222222222222 ; ?
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ExtraPush: dq 0x3333333333333333 ; ?
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ExceptData: dq 0x4444444444444444 ; ?
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Rflags: dq 0x5555555555555555 ; ?
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ASM_PFX(OrigVector): dq 0x6666666666666666 ; ?
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;; The declarations below define the memory region that will be used for the debug stack.
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;; The context record will be built by pushing register values onto this stack.
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;; It is imparitive that alignment be carefully managed, since the FXSTOR and
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;; FXRSTOR instructions will GP fault if their memory operand is not 16 byte aligned.
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;;
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;; The stub will switch stacks from the application stack to the debuger stack
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;; and pushes the exception number.
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;;
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;; Then we building the context record on the stack. Since the stack grows down,
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;; we push the fields of the context record from the back to the front. There
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;; are 336 bytes of stack used prior allocating the 512 bytes of stack to be
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;; used as the memory buffer for the fxstor instruction. Therefore address of
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;; the buffer used for the FXSTOR instruction is &Eax - 336 - 512, which
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;; must be 16 byte aligned.
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;;
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;; We carefully locate the stack to make this happen.
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;;
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;; For reference, the context structure looks like this:
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;; struct {
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;; UINT64 ExceptionData;
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;; FX_SAVE_STATE_X64 FxSaveState; // 512 bytes, must be 16 byte aligned
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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;; UINT64 RFlags;
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;; UINT64 Ldtr, Tr;
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;; UINT64 Gdtr[2], Idtr[2];
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;; UINT64 Rip;
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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;; } SYSTEM_CONTEXT_X64; // 64 bit system context record
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align 16
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DebugStackEnd: db "DbgStkEnd >>>>>>" ;; 16 byte long string - must be 16 bytes to preserve alignment
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times 0x1ffc dd 0x0 ;; 32K should be enough stack
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;; This allocation is coocked to insure
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;; that the the buffer for the FXSTORE instruction
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;; will be 16 byte aligned also.
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;;
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ExceptionNumber: dq 0 ;; first entry will be the vector number pushed by the stub
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DebugStackBegin: db "<<<< DbgStkBegin" ;; initial debug ESP == DebugStackBegin, set in stub
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; BOOLEAN
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; FxStorSupport (
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; void
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; )
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;
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; Abstract: Returns TRUE if FxStor instructions are supported
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;
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global ASM_PFX(FxStorSupport)
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ASM_PFX(FxStorSupport):
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;
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; cpuid corrupts rbx which must be preserved per the C calling convention
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;
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push rbx
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mov rax, dword 1
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cpuid
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mov eax, edx
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and rax, FXSTOR_FLAG
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shr rax, 24
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pop rbx
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ret
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;------------------------------------------------------------------------------
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; void
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; Vect2Desc (
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; IA32_IDT_GATE_DESCRIPTOR * DestDesc, // rcx
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; void (*Vector) (void) // rdx
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; )
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;
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; Abstract: Encodes an IDT descriptor with the given physical address
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;
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global ASM_PFX(Vect2Desc)
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ASM_PFX(Vect2Desc):
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mov rax, rdx
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mov word [rcx], ax ; write bits 15..0 of offset
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mov dx, cs
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mov word [rcx+2], dx ; SYS_CODE_SEL from GDT
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mov word [rcx+4], 0xe00 | 0x8000 ; type = 386 interrupt gate, present
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shr rax, 16
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mov word [rcx+6], ax ; write bits 31..16 of offset
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shr rax, 16
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mov dword [rcx+8], eax ; write bits 63..32 of offset
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ret
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;------------------------------------------------------------------------------
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; InterruptEntryStub
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;
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; Abstract: This code is not a function, but is a small piece of code that is
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; copied and fixed up once for each IDT entry that is hooked.
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;
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ASM_PFX(InterruptEntryStub):
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push 0 ; push vector number - will be modified before installed
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db 0xe9 ; jump rel32
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dd 0 ; fixed up to relative address of CommonIdtEntry
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InterruptEntryStubEnd:
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;------------------------------------------------------------------------------
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; CommonIdtEntry
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;
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; Abstract: This code is not a function, but is the common part for all IDT
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; vectors.
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;
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ASM_PFX(CommonIdtEntry):
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;;
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;; At this point, the stub has saved the current application stack esp into AppRsp
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;; and switched stacks to the debug stack, where it pushed the vector number
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;;
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;; The application stack looks like this:
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;;
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;; ...
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;; (last application stack entry)
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;; [16 bytes alignment, do not care it]
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;; SS from interrupted task
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;; RSP from interrupted task
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;; rflags from interrupted task
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;; CS from interrupted task
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;; RIP from interrupted task
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;; Error code <-------------------- Only present for some exeption types
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;;
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;; Vector Number <----------------- pushed in our IDT Entry
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;;
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;; The stub switched us to the debug stack and pushed the interrupt number.
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;;
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;; Next, construct the context record. It will be build on the debug stack by
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;; pushing the registers in the correct order so as to create the context structure
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;; on the debug stack. The context record must be built from the end back to the
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;; beginning because the stack grows down...
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;
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;; For reference, the context record looks like this:
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;;
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;; typedef
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;; struct {
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;; UINT64 ExceptionData;
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;; FX_SAVE_STATE_X64 FxSaveState;
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; UINT64 Cr0, Cr2, Cr3, Cr4, Cr8;
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;; UINT64 RFlags;
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;; UINT64 Ldtr, Tr;
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;; UINT64 Gdtr[2], Idtr[2];
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;; UINT64 Rip;
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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;; } SYSTEM_CONTEXT_X64; // 64 bit system context record
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;; NOTE: we save rsp here to prevent compiler put rip reference cause error AppRsp
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push rax
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mov rax, qword [rsp+8] ; save vector number
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mov [ExceptionNumber], rax ; save vector number
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pop rax
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add rsp, 8 ; pop vector number
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mov [AppRsp], rsp ; save stack top
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lea rsp, [DebugStackBegin] ; switch to debugger stack
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sub rsp, 8 ; leave space for vector number
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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push r15
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push r14
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push r13
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push r12
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push r11
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push r10
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push r9
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push r8
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push rax
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push rcx
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push rdx
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push rbx
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push rsp
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push rbp
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push rsi
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push rdi
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;; Save interrupt state rflags register...
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pushfq
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pop rax
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mov [Rflags], rax
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;; We need to determine if any extra data was pushed by the exception, and if so, save it
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;; To do this, we check the exception number pushed by the stub, and cache the
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;; result in a variable since we'll need this again.
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cmp qword [ExceptionNumber], EXCPT64_DOUBLE_FAULT
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jz ExtraPushOne
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cmp qword [ExceptionNumber], EXCPT64_INVALID_TSS
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jz ExtraPushOne
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cmp qword [ExceptionNumber], EXCPT64_SEG_NOT_PRESENT
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jz ExtraPushOne
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cmp qword [ExceptionNumber], EXCPT64_STACK_FAULT
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jz ExtraPushOne
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cmp qword [ExceptionNumber], EXCPT64_GP_FAULT
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jz ExtraPushOne
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cmp qword [ExceptionNumber], EXCPT64_PAGE_FAULT
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jz ExtraPushOne
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cmp qword [ExceptionNumber], EXCPT64_ALIGNMENT_CHECK
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jz ExtraPushOne
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mov qword [ExtraPush], 0
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mov qword [ExceptData], 0
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jmp ExtraPushDone
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ExtraPushOne:
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mov qword [ExtraPush], 1
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;; If there's some extra data, save it also, and modify the saved AppRsp to effectively
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;; pop this value off the application's stack.
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mov rax, [AppRsp]
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mov rbx, [rax]
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mov qword [ExceptData], rbx
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add rax, 8
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mov [AppRsp], rax
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ExtraPushDone:
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;; The "push" above pushed the debug stack rsp. Since what we're actually doing
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;; is building the context record on the debug stack, we need to save the pushed
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;; debug RSP, and replace it with the application's last stack entry...
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mov rax, [rsp + 24]
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mov [DebugRsp], rax
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mov rax, [AppRsp]
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mov rax, QWORD [rax + 24]
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; application stack has ss, rsp, rflags, cs, & rip, so
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; last actual application stack entry is saved at offset
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; 24 bytes from stack top.
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mov [rsp + 24], rax
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;; continue building context record
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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mov rax, ss
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push rax
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; CS from application is one entry back in application stack
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mov rax, [AppRsp]
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movzx rax, word [rax + 8]
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push rax
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mov rax, ds
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push rax
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mov rax, es
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push rax
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mov rax, fs
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push rax
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mov rax, gs
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push rax
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;; UINT64 Rip;
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; Rip from application is on top of application stack
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mov rax, [AppRsp]
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push qword [rax]
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;; UINT64 Gdtr[2], Idtr[2];
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push 0
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push 0
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sidt [rsp]
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push 0
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push 0
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sgdt [rsp]
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;; UINT64 Ldtr, Tr;
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xor rax, rax
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str ax
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push rax
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sldt ax
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push rax
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;; UINT64 RFlags;
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;; Rflags from application is two entries back in application stack
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mov rax, [AppRsp]
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push qword [rax + 16]
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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;; insure FXSAVE/FXRSTOR is enabled in CR4...
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;; ... while we're at it, make sure DE is also enabled...
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mov rax, cr8
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push rax
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mov rax, cr4
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or rax, 0x208
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mov cr4, rax
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push rax
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mov rax, cr3
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push rax
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mov rax, cr2
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push rax
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push 0
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mov rax, cr0
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push rax
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov rax, dr7
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push rax
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;; clear Dr7 while executing debugger itself
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xor rax, rax
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mov dr7, rax
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mov rax, dr6
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push rax
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;; insure all status bits in dr6 are clear...
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xor rax, rax
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mov dr6, rax
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mov rax, dr3
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push rax
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mov rax, dr2
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push rax
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mov rax, dr1
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push rax
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mov rax, dr0
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push rax
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;; FX_SAVE_STATE_X64 FxSaveState;
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sub rsp, 512
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mov rdi, rsp
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; IMPORTANT!! The debug stack has been carefully constructed to
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; insure that rsp and rdi are 16 byte aligned when we get here.
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; They MUST be. If they are not, a GP fault will occur.
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fxsave [rdi]
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;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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cld
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;; UINT64 ExceptionData;
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mov rax, [ExceptData]
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push rax
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; call to C code which will in turn call registered handler
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; pass in the vector number
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mov rdx, rsp
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mov rcx, [ExceptionNumber]
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sub rsp, 40
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call ASM_PFX(InterruptDistrubutionHub)
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add rsp, 40
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; restore context...
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;; UINT64 ExceptionData;
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add rsp, 8
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;; FX_SAVE_STATE_X64 FxSaveState;
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mov rsi, rsp
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fxrstor [rsi]
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add rsp, 512
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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pop rax
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mov dr0, rax
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pop rax
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mov dr1, rax
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pop rax
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mov dr2, rax
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pop rax
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mov dr3, rax
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;; skip restore of dr6. We cleared dr6 during the context save.
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add rsp, 8
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pop rax
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mov dr7, rax
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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pop rax
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mov cr0, rax
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add rsp, 8
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pop rax
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mov cr2, rax
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pop rax
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mov cr3, rax
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pop rax
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mov cr4, rax
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pop rax
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mov cr8, rax
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;; UINT64 RFlags;
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mov rax, [AppRsp]
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pop qword [rax + 16]
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;; UINT64 Ldtr, Tr;
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;; UINT64 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add rsp, 48
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;; UINT64 Rip;
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pop qword [rax]
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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;; NOTE - modified segment registers could hang the debugger... We
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;; could attempt to insulate ourselves against this possibility,
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;; but that poses risks as well.
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;;
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pop rax
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; mov gs, rax
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pop rax
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; mov fs, rax
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pop rax
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mov es, rax
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pop rax
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mov ds, rax
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mov rax, [AppRsp]
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pop qword [rax + 8]
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pop rax
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mov ss, rax
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;; The next stuff to restore is the general purpose registers that were pushed
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;; using the "push" instruction.
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;;
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;; The value of RSP as stored in the context record is the application RSP
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;; including the 5 entries on the application stack caused by the exception
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;; itself. It may have been modified by the debug agent, so we need to
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;; determine if we need to relocate the application stack.
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mov rbx, [rsp + 24] ; move the potentially modified AppRsp into rbx
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mov rax, [AppRsp]
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mov rax, QWORD [rax + 24]
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cmp rbx, rax
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je NoAppStackMove
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mov rax, [AppRsp]
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mov rcx, [rax] ; RIP
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mov [rbx], rcx
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mov rcx, [rax + 8] ; CS
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mov [rbx + 8], rcx
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mov rcx, [rax + 16] ; RFLAGS
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mov [rbx + 16], rcx
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mov rcx, [rax + 24] ; RSP
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mov [rbx + 24], rcx
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mov rcx, [rax + 32] ; SS
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mov [rbx + 32], rcx
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mov rax, rbx ; modify the saved AppRsp to the new AppRsp
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mov [AppRsp], rax
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NoAppStackMove:
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mov rax, [DebugRsp] ; restore the DebugRsp on the debug stack
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; so our "pop" will not cause a stack switch
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mov [rsp + 24], rax
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cmp qword [ExceptionNumber], 0x68
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jne NoChain
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Chain:
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;; Restore rflags so when we chain, the flags will be exactly as if we were never here.
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;; We gin up the stack to do an iretq so we can get ALL the flags.
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mov rax, [AppRsp]
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mov rbx, [rax + 40]
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push rbx
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mov rax, ss
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push rax
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mov rax, rsp
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add rax, 16
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push rax
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mov rax, [AppRsp]
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mov rbx, [rax + 16]
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and rbx, ~ 0x300 ; special handling for IF and TF
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push rbx
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mov rax, cs
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push rax
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lea rax, [PhonyIretq]
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push rax
|
|
iretq
|
|
PhonyIretq:
|
|
|
|
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
|
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
|
pop rdi
|
|
pop rsi
|
|
pop rbp
|
|
pop rsp
|
|
pop rbx
|
|
pop rdx
|
|
pop rcx
|
|
pop rax
|
|
pop r8
|
|
pop r9
|
|
pop r10
|
|
pop r11
|
|
pop r12
|
|
pop r13
|
|
pop r14
|
|
pop r15
|
|
|
|
;; Switch back to application stack
|
|
mov rsp, [AppRsp]
|
|
|
|
;; Jump to original handler
|
|
jmp [ASM_PFX(OrigVector)]
|
|
|
|
NoChain:
|
|
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
|
|
;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
|
|
pop rdi
|
|
pop rsi
|
|
pop rbp
|
|
pop rsp
|
|
pop rbx
|
|
pop rdx
|
|
pop rcx
|
|
pop rax
|
|
pop r8
|
|
pop r9
|
|
pop r10
|
|
pop r11
|
|
pop r12
|
|
pop r13
|
|
pop r14
|
|
pop r15
|
|
|
|
;; Switch back to application stack
|
|
mov rsp, [AppRsp]
|
|
|
|
;; We're outa here...
|
|
iretq
|
|
|