a37f660599
This adds ARM support to BaseMemoryLibOptDxe, partially based on the cortex-strings library (ScanMem) and the existing CopyMem() implementation from BaseMemoryLibStm in ArmPkg. All string routines are accelerated except ScanMem16, ScanMem32, ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few occurrences exist in the codebase) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
141 lines
4.7 KiB
NASM
141 lines
4.7 KiB
NASM
;
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; Copyright (c) 2013 - 2016, Linaro Limited
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; * Neither the name of the Linaro nor the
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; names of its contributors may be used to endorse or promote products
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; derived from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; Parameters and result.
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#define src1 r0
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#define src2 r1
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#define limit r2
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#define result r0
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; Internal variables.
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#define data1 r3
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#define data2 r4
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#define limit_wd r5
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#define diff r6
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#define tmp1 r7
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#define tmp2 r12
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#define pos r8
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#define mask r14
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EXPORT InternalMemCompareMem
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THUMB
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AREA CompareMem, CODE, READONLY
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InternalMemCompareMem
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push {r4-r8, lr}
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eor tmp1, src1, src2
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tst tmp1, #3
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bne Lmisaligned4
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ands tmp1, src1, #3
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bne Lmutual_align
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add limit_wd, limit, #3
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nop.w
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lsr limit_wd, limit_wd, #2
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; Start of performance-critical section -- one 32B cache line.
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Lloop_aligned
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ldr data1, [src1], #4
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ldr data2, [src2], #4
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Lstart_realigned
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subs limit_wd, limit_wd, #1
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eor diff, data1, data2 ; Non-zero if differences found.
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cbnz diff, L0
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bne Lloop_aligned
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; End of performance-critical section -- one 32B cache line.
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; Not reached the limit, must have found a diff.
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L0
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cbnz limit_wd, Lnot_limit
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// Limit % 4 == 0 => all bytes significant.
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ands limit, limit, #3
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beq Lnot_limit
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lsl limit, limit, #3 // Bits -> bytes.
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mov mask, #~0
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lsl mask, mask, limit
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bic data1, data1, mask
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bic data2, data2, mask
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orr diff, diff, mask
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Lnot_limit
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rev diff, diff
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rev data1, data1
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rev data2, data2
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; The MS-non-zero bit of DIFF marks either the first bit
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; that is different, or the end of the significant data.
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; Shifting left now will bring the critical information into the
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; top bits.
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clz pos, diff
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lsl data1, data1, pos
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lsl data2, data2, pos
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; But we need to zero-extend (char is unsigned) the value and then
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; perform a signed 32-bit subtraction.
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lsr data1, data1, #28
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sub result, data1, data2, lsr #28
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pop {r4-r8, pc}
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Lmutual_align
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; Sources are mutually aligned, but are not currently at an
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; alignment boundary. Round down the addresses and then mask off
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; the bytes that precede the start point.
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bic src1, src1, #3
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bic src2, src2, #3
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add limit, limit, tmp1 ; Adjust the limit for the extra.
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lsl tmp1, tmp1, #2 ; Bytes beyond alignment -> bits.
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ldr data1, [src1], #4
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neg tmp1, tmp1 ; Bits to alignment -32.
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ldr data2, [src2], #4
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mov tmp2, #~0
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; Little-endian. Early bytes are at LSB.
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lsr tmp2, tmp2, tmp1 ; Shift (tmp1 & 31).
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add limit_wd, limit, #3
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orr data1, data1, tmp2
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orr data2, data2, tmp2
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lsr limit_wd, limit_wd, #2
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b Lstart_realigned
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Lmisaligned4
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sub limit, limit, #1
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L1
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// Perhaps we can do better than this.
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ldrb data1, [src1], #1
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ldrb data2, [src2], #1
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subs limit, limit, #1
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it cs
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cmpcs data1, data2
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beq L1
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sub result, data1, data2
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pop {r4-r8, pc}
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END
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