599f4a4ddd
EDK2 expects PCI bars to be continously be allocated without "gaps" of reserverd memory in between. coreboot places PCI bars anyware in the PCI MMIO space, interleaved with MMCONF and reserved I/O MMIO space. Warn about this behaviour and refuse to add the BAR to the PCI aperature as it would cause the PciHostBridgeDxe fo fail. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
43 lines
998 B
INI
43 lines
998 B
INI
## @file
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# Library instance of PciHostBridgeLib library class for coreboot.
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#
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# Copyright (C) 2016, Red Hat, Inc.
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# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = PciHostBridgeLib
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FILE_GUID = 62EE5269-CFFD-43a3-BE3F-622FC79F467E
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = PciHostBridgeLib
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#
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# The following information is for reference only and not required by the build
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# tools.
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#
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# VALID_ARCHITECTURES = IA32 X64 EBC
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#
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[Sources]
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PciHostBridge.h
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PciHostBridgeLib.c
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PciHostBridgeSupport.c
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[Packages]
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MdeModulePkg/MdeModulePkg.dec
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MdePkg/MdePkg.dec
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[LibraryClasses]
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BaseMemoryLib
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DebugLib
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DevicePathLib
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MemoryAllocationLib
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PciLib
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DxeServicesTableLib
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