a44fef7de3
The data type used by variables representing the GicInterruptInterfaceBase has been inconsistently used in the ArmGic driver and the library. The PCD defined for the GIC Interrupt interface base address is UINT64. However, the data types for the variables used is UINTN, INTN, and at some places UINT32. Therefore, update the data types to use UINTN and add necessary typecasts when reading values from the PCD. This should then be consistent across AArch32 and AArch64 builds. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
336 lines
9.1 KiB
C
336 lines
9.1 KiB
C
/** @file
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*
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* Copyright (c) 2011-2023, Arm Limited. All rights reserved.<BR>
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef ARMGIC_H_
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#define ARMGIC_H_
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#include <Library/ArmGicArchLib.h>
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// GIC Distributor
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#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
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#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
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#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
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// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
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#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
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#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
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#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
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#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
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#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
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#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
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// Each reg base below repeats for Number of interrupts / 4
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#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
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// Each reg base below repeats for Number of interrupts
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#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
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#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
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#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
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// just one of these
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#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
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// GICv3 specific registers
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#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
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// GICD_CTLR bits
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#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
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#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
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// GICD_ICDICFR bits
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#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
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#define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8)
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#define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits
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#define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register
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#define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field
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#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
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#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
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// GIC Redistributor
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#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
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#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
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// GIC Redistributor Control frame
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#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
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// GIC Redistributor TYPER bit assignments
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#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
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#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
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#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
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#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
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#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
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// Selection Support
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#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
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#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
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#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
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#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
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ARM_GICR_TYPER_AFFINITY) >> 32)
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// GIC SGI & PPI Redistributor frame
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#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
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#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
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// GIC Cpu interface
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#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
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#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
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#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
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#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
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#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
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#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
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#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
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#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
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#define ARM_GIC_ICCIIDR 0xFC // Identification Register
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#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
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#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
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#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
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// Bit-masks to configure the CPU Interface Control register
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#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
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#define ARM_GIC_ICCICR_ENABLE_NS 0x02
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#define ARM_GIC_ICCICR_ACK_CTL 0x04
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#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
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#define ARM_GIC_ICCICR_USE_SBPR 0x10
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// Bit Mask for GICC_IIDR
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#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
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#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
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#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
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#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
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// Bit Mask for
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#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
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UINTN
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EFIAPI
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ArmGicGetInterfaceIdentification (
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IN UINTN GicInterruptInterfaceBase
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);
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// GIC Secure interfaces
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VOID
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EFIAPI
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ArmGicSetupNonSecure (
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IN UINTN MpId,
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IN UINTN GicDistributorBase,
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicSetSecureInterrupts (
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IN UINTN GicDistributorBase,
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IN UINTN *GicSecureInterruptMask,
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IN UINTN GicSecureInterruptMaskSize
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);
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VOID
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EFIAPI
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ArmGicEnableInterruptInterface (
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicDisableInterruptInterface (
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicEnableDistributor (
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IN UINTN GicDistributorBase
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);
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VOID
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EFIAPI
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ArmGicDisableDistributor (
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IN UINTN GicDistributorBase
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);
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UINTN
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EFIAPI
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ArmGicGetMaxNumInterrupts (
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IN UINTN GicDistributorBase
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);
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VOID
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EFIAPI
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ArmGicSendSgiTo (
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IN UINTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList,
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IN INTN SgiId
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);
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/*
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* Acknowledge and return the value of the Interrupt Acknowledge Register
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*
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* InterruptId is returned separately from the register value because in
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* the GICv2 the register value contains the CpuId and InterruptId while
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* in the GICv3 the register value is only the InterruptId.
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*
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* @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
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* @param InterruptId InterruptId read from the Interrupt
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* Acknowledge Register
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*
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* @retval value returned by the Interrupt Acknowledge Register
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*
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*/
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UINTN
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EFIAPI
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ArmGicAcknowledgeInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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OUT UINTN *InterruptId
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);
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VOID
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EFIAPI
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ArmGicEndOfInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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IN UINTN Source
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);
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UINTN
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EFIAPI
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ArmGicSetPriorityMask (
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IN UINTN GicInterruptInterfaceBase,
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IN INTN PriorityMask
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);
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VOID
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EFIAPI
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ArmGicSetInterruptPriority (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source,
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IN UINTN Priority
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);
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VOID
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EFIAPI
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ArmGicEnableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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);
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VOID
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EFIAPI
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ArmGicDisableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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);
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BOOLEAN
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EFIAPI
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ArmGicIsInterruptEnabled (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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);
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// GIC revision 2 specific declarations
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// Interrupts from 1020 to 1023 are considered as special interrupts
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// (eg: spurious interrupts)
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#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
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(((Interrupt) >= 1020) && ((Interrupt) <= 1023))
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VOID
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EFIAPI
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ArmGicV2SetupNonSecure (
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IN UINTN MpId,
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IN UINTN GicDistributorBase,
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicV2EnableInterruptInterface (
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicV2DisableInterruptInterface (
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IN UINTN GicInterruptInterfaceBase
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);
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UINTN
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EFIAPI
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ArmGicV2AcknowledgeInterrupt (
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IN UINTN GicInterruptInterfaceBase
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);
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VOID
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EFIAPI
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ArmGicV2EndOfInterrupt (
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IN UINTN GicInterruptInterfaceBase,
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IN UINTN Source
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);
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// GIC revision 3 specific declarations
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#define ICC_SRE_EL2_SRE (1 << 0)
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#define ARM_GICD_IROUTER_IRM BIT31
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UINT32
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EFIAPI
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ArmGicV3GetControlSystemRegisterEnable (
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VOID
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);
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VOID
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EFIAPI
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ArmGicV3SetControlSystemRegisterEnable (
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IN UINT32 ControlSystemRegisterEnable
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);
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VOID
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EFIAPI
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ArmGicV3EnableInterruptInterface (
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VOID
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);
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VOID
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EFIAPI
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ArmGicV3DisableInterruptInterface (
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VOID
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);
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UINTN
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EFIAPI
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ArmGicV3AcknowledgeInterrupt (
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VOID
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);
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VOID
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EFIAPI
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ArmGicV3EndOfInterrupt (
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IN UINTN Source
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);
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VOID
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ArmGicV3SetBinaryPointer (
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IN UINTN BinaryPoint
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);
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VOID
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ArmGicV3SetPriorityMask (
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IN UINTN Priority
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);
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#endif // ARMGIC_H_
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