a6caee65ac
The PcdStandalone is a PCD ARM Ltd uses to make the difference between a standalone UEFI (boot from cold boot to Boot Manager without user intervention) and a Debug UEFI firmware (the firmware engineer has to copy the Normale World image into the DRAM to enable his/her firmware). By coping the firmware into DRAM in the non standalone version it is much faster than reflashing the NOR Flash after each build. ArmPlatformSecExtraAction() function is called just before the Sec module jump to normal world. The platform firmware can run extra actions at this stage. The 'ARM Standalone' concept has moved to the implementation of ArmPlatformSecExtraAction() for the ARM development boards (in ArmPlatformPkg/Library/DebugSecExtraActionLib). ArmPlatformPkg: Enable DebugAgentLib in Sec and PrePeiCore ArmPlatformPkg: Fix line endings in some source files Use CR+LF line endings as defined by the EDK2 coding convention git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11991 6f19259b-4bc3-4df7-8a09-765794883524
56 lines
1.4 KiB
ArmAsm
Executable File
56 lines
1.4 KiB
ArmAsm
Executable File
#------s------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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GCC_ASM_EXPORT(__aeabi_ulcmp)
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ASM_PFX(__aeabi_ulcmp):
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stmfd sp!, {r4, r5, r8}
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cmp r3, r1
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mov r8, r0
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mov r9, r1
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mov r4, r2
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mov r5, r3
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bls L16
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L2:
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mvn r0, #0
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L1:
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ldmfd sp!, {r4, r5, r8}
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bx lr
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L16:
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beq L17
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L4:
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cmp r9, r5
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bhi L7
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beq L18
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cmp r8, r4
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L14:
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cmpeq r9, r5
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moveq r0, #0
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beq L1
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b L1
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L18:
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cmp r8, r4
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bls L14
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L7:
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mov r0, #1
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b L1
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L17:
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cmp r2, r0
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bhi L2
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b L4
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