a6caee65ac
The PcdStandalone is a PCD ARM Ltd uses to make the difference between a standalone UEFI (boot from cold boot to Boot Manager without user intervention) and a Debug UEFI firmware (the firmware engineer has to copy the Normale World image into the DRAM to enable his/her firmware). By coping the firmware into DRAM in the non standalone version it is much faster than reflashing the NOR Flash after each build. ArmPlatformSecExtraAction() function is called just before the Sec module jump to normal world. The platform firmware can run extra actions at this stage. The 'ARM Standalone' concept has moved to the implementation of ArmPlatformSecExtraAction() for the ARM development boards (in ArmPlatformPkg/Library/DebugSecExtraActionLib). ArmPlatformPkg: Enable DebugAgentLib in Sec and PrePeiCore ArmPlatformPkg: Fix line endings in some source files Use CR+LF line endings as defined by the EDK2 coding convention git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11991 6f19259b-4bc3-4df7-8a09-765794883524
95 lines
3.4 KiB
C
95 lines
3.4 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmMPCoreMailBoxLib.h>
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#include <Chipset/ArmV7.h>
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#include <Drivers/PL390Gic.h>
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#include "PrePeiCore.h"
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extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
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/*
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* This is the main function for secondary cores. They loop around until a non Null value is written to
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* SYS_FLAGS register.The SYS_FLAGS register is platform specific.
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* Note:The secondary cores, while executing secondary_main, assumes that:
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* : SGI 0 is configured as Non-secure interrupt
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* : Priority Mask is configured to allow SGI 0
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* : Interrupt Distributor and CPU interfaces are enabled
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*
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*/
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN CoreId
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)
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{
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// Function pointer to Secondary Core entry point
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VOID (*secondary_start)(VOID);
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UINTN secondary_entry_addr=0;
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// Clear Secondary cores MailBox
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ArmClearMPCoreMailbox();
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while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
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}
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secondary_start = (VOID (*)())secondary_entry_addr;
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// Jump to secondary core entry point.
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secondary_start();
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// The secondaries shouldn't reach here
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ASSERT(FALSE);
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}
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VOID
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EFIAPI
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PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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//Enable the GIC Distributor
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PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
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// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
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if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) {
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// Sending SGI to all the Secondary CPU interfaces
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PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
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SecCoreData.StackBase = SecCoreData.TemporaryRamBase;
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SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
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// Jump to PEI core entry point
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(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
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}
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