a75568e9c9
For instance, in case of CpuHotPlug boot path the platform has already been initialized. The CPU core should not execute any of the platform initialization in this case. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13492 6f19259b-4bc3-4df7-8a09-765794883524
126 lines
4.3 KiB
ArmAsm
126 lines
4.3 KiB
ArmAsm
//
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AutoGen.h>
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#include <AsmMacroIoLib.h>
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#include "SecInternal.h"
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.text
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.align 3
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GCC_ASM_IMPORT(CEntryPoint)
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GCC_ASM_IMPORT(ArmPlatformSecBootAction)
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GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
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GCC_ASM_IMPORT(ArmDisableInterrupts)
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GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
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GCC_ASM_IMPORT(ArmWriteVBar)
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GCC_ASM_IMPORT(ArmReadMpidr)
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GCC_ASM_IMPORT(SecVectorTable)
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GCC_ASM_IMPORT(ArmCallWFE)
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GCC_ASM_EXPORT(_ModuleEntryPoint)
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StartupAddr: .word ASM_PFX(CEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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// First ensure all interrupts are disabled
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bl ASM_PFX(ArmDisableInterrupts)
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// Ensure that the MMU and caches are off
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bl ASM_PFX(ArmDisableCachesAndMmu)
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// By default, we are doing a cold boot
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mov r10, #ARM_SEC_COLD_BOOT
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// Jump to Platform Specific Boot Action function
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blx ASM_PFX(ArmPlatformSecBootAction)
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// Set VBAR to the start of the exception vectors in Secure Mode
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LoadConstantToReg (ASM_PFX(SecVectorTable), r0)
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bl ASM_PFX(ArmWriteVBar)
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_IdentifyCpu:
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// Identify CPU ID
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bl ASM_PFX(ArmReadMpidr)
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// Get ID of this CPU in Multicore system
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LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
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and r5, r0, r1
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// Is it the Primary Core ?
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LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
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cmp r5, r3
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// Only the primary core initialize the memory (SMC)
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beq _InitMem
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_WaitInitMem:
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// If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
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// Otherwise we have to wait the Primary Core to finish the initialization
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cmp r10, #ARM_SEC_COLD_BOOT
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bne _SetupSecondaryCoreStack
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// Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
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bl ASM_PFX(ArmCallWFE)
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// Now the Init Mem is initialized, we setup the secondary core stacks
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b _SetupSecondaryCoreStack
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_InitMem:
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// Initialize Init Boot Memory
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bl ASM_PFX(ArmPlatformSecBootMemoryInit)
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// Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
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LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
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_SetupPrimaryCoreStack:
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// Get the top of the primary stacks (and the base of the secondary stacks)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
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add r1, r1, r2
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LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
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// The reserved space for global variable must be 8-bytes aligned for pushing
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// 64-bit variable on the stack
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SetPrimaryStack (r1, r2, r3)
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b _PrepareArguments
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_SetupSecondaryCoreStack:
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// Get the top of the primary stacks (and the base of the secondary stacks)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
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add r1, r1, r2
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// Get the Core Position (ClusterId * 4) + CoreId
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GetCorePositionInStack(r0, r5, r2)
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// The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
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add r0, r0, #1
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// StackOffset = CorePos * StackSize
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
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mul r0, r0, r2
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// SP = StackBase + StackOffset
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add sp, r1, r0
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_PrepareArguments:
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// Move sec startup address into a data register
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// Ensure we're jumping to FV version of the code (not boot remapped alias)
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ldr r3, StartupAddr
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// Jump to SEC C code
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// r0 = mp_id
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// r1 = Boot Mode
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mov r0, r5
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mov r1, r10
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blx r3
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_NeverReturn:
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b _NeverReturn
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