a8c791c15b
Add a new entry point for Xen PVH that enter directly in 32bits.
Information on the expected state of the machine when this entry point
is used can be found at:
https://xenbits.xenproject.org/docs/unstable/misc/pvh.html
Also, compare to the original file [1], the two `nop' of the "resetVector"
entry point are removed. There were introduced by 8332983e2e
("UefiCpuPkg: Replace the un-necessary WBINVD instruction at the reset
vector with two NOPs in VTF0.", 2011-08-04), but don't seems to be
useful. This is the entry point used by HVM guest (hvmloader).
[1] UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1689
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20190813113119.14804-7-anthony.perard@citrix.com>
50 lines
1.1 KiB
NASM
50 lines
1.1 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; An entry point use by Xen when a guest is started in PVH mode.
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;
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; Copyright (c) 2019, Citrix Systems, Inc.
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;
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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xenPVHMain:
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;
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; 'BP' to indicate boot-strap processor
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;
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mov di, 'BP'
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;
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; ESP will be used as initial value of the EAX register
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; in Main.asm
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;
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xor esp, esp
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mov ebx, ADDR_OF(gdtr)
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lgdt [ebx]
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mov eax, SEC_DEFAULT_CR0
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mov cr0, eax
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jmp LINEAR_CODE_SEL:ADDR_OF(.jmpToNewCodeSeg)
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.jmpToNewCodeSeg:
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mov eax, SEC_DEFAULT_CR4
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mov cr4, eax
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mov ax, LINEAR_SEL
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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;
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; Jump to the main routine of the pre-SEC code
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; skiping the 16-bit part of the routine and
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; into the 32-bit flat mode part
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;
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OneTimeCallRet TransitionFromReal16To32BitFlat
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