ada4a003f9
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Previously, when compiling NASM source files, BaseTools did not support including files outside of the NASM source file directory. As a result, we duplicated multiple copies of "StuffRsb.inc" files in UefiCpuPkg. Those INC files contain the common logic to stuff the Return Stack Buffer and are identical. After the fix of BZ 1085: https://bugzilla.tianocore.org/show_bug.cgi?id=1085 The above support was introduced. Thus, this commit will merge all the StuffRsb.inc files in UefiCpuPkg into one file. The merged file will be named 'StuffRsbNasm.inc' and be placed under folder UefiCpuPkg/Include/. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
103 lines
3.1 KiB
NASM
103 lines
3.1 KiB
NASM
;------------------------------------------------------------------------------ ;
|
|
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
|
|
; This program and the accompanying materials
|
|
; are licensed and made available under the terms and conditions of the BSD License
|
|
; which accompanies this distribution. The full text of the license may be found at
|
|
; http://opensource.org/licenses/bsd-license.php.
|
|
;
|
|
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
|
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|
;
|
|
; Module Name:
|
|
;
|
|
; SmmInit.nasm
|
|
;
|
|
; Abstract:
|
|
;
|
|
; Functions for relocating SMBASE's for all processors
|
|
;
|
|
;-------------------------------------------------------------------------------
|
|
|
|
%include "StuffRsbNasm.inc"
|
|
|
|
extern ASM_PFX(SmmInitHandler)
|
|
extern ASM_PFX(mRebasedFlag)
|
|
extern ASM_PFX(mSmmRelocationOriginalAddress)
|
|
|
|
global ASM_PFX(gPatchSmmCr3)
|
|
global ASM_PFX(gPatchSmmCr4)
|
|
global ASM_PFX(gPatchSmmCr0)
|
|
global ASM_PFX(gPatchSmmInitStack)
|
|
global ASM_PFX(gcSmiInitGdtr)
|
|
global ASM_PFX(gcSmmInitSize)
|
|
global ASM_PFX(gcSmmInitTemplate)
|
|
|
|
%define PROTECT_MODE_CS 0x8
|
|
%define PROTECT_MODE_DS 0x20
|
|
|
|
SECTION .text
|
|
|
|
ASM_PFX(gcSmiInitGdtr):
|
|
DW 0
|
|
DQ 0
|
|
|
|
global ASM_PFX(SmmStartup)
|
|
|
|
BITS 16
|
|
ASM_PFX(SmmStartup):
|
|
mov eax, 0x80000001 ; read capability
|
|
cpuid
|
|
mov ebx, edx ; rdmsr will change edx. keep it in ebx.
|
|
and ebx, BIT20 ; extract NX capability bit
|
|
shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position
|
|
mov eax, strict dword 0 ; source operand will be patched
|
|
ASM_PFX(gPatchSmmCr3):
|
|
mov cr3, eax
|
|
o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
|
|
mov eax, strict dword 0 ; source operand will be patched
|
|
ASM_PFX(gPatchSmmCr4):
|
|
mov cr4, eax
|
|
mov ecx, 0xc0000080 ; IA32_EFER MSR
|
|
rdmsr
|
|
or eax, ebx ; set NXE bit if NX is available
|
|
wrmsr
|
|
mov eax, strict dword 0 ; source operand will be patched
|
|
ASM_PFX(gPatchSmmCr0):
|
|
mov di, PROTECT_MODE_DS
|
|
mov cr0, eax
|
|
jmp PROTECT_MODE_CS : dword @32bit
|
|
|
|
BITS 32
|
|
@32bit:
|
|
mov ds, edi
|
|
mov es, edi
|
|
mov fs, edi
|
|
mov gs, edi
|
|
mov ss, edi
|
|
mov esp, strict dword 0 ; source operand will be patched
|
|
ASM_PFX(gPatchSmmInitStack):
|
|
call ASM_PFX(SmmInitHandler)
|
|
StuffRsb32
|
|
rsm
|
|
|
|
BITS 16
|
|
ASM_PFX(gcSmmInitTemplate):
|
|
mov ebp, ASM_PFX(SmmStartup)
|
|
sub ebp, 0x30000
|
|
jmp ebp
|
|
|
|
ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
|
|
|
|
BITS 32
|
|
global ASM_PFX(SmmRelocationSemaphoreComplete)
|
|
ASM_PFX(SmmRelocationSemaphoreComplete):
|
|
push eax
|
|
mov eax, [ASM_PFX(mRebasedFlag)]
|
|
mov byte [eax], 1
|
|
pop eax
|
|
jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
|
|
|
|
global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
|
|
ASM_PFX(PiSmmCpuSmmInitFixupAddress):
|
|
ret
|