f0abe42fd7
Fix GCC issue on FspInfoHeaderRelativeOff. Clean up comments for platform ID matching on Microcode and PcdFspBootFirmwareVolumeBase Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17496 6f19259b-4bc3-4df7-8a09-765794883524
814 lines
21 KiB
ArmAsm
814 lines
21 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Abstract:
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#
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# Provide FSP API entry points.
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#
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#------------------------------------------------------------------------------
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.equ MSR_IA32_PLATFORM_ID, 0x00000017
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.equ MSR_IA32_BIOS_UPDT_TRIG, 0x00000079
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.equ MSR_IA32_BIOS_SIGN_ID, 0x0000008b
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MicrocodeHdr:
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.equ MicrocodeHdrVersion, 0x0000
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.equ MicrocodeHdrRevision, 0x0004
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.equ MicrocodeHdrDate, 0x0008
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.equ MicrocodeHdrProcessor, 0x000c
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.equ MicrocodeHdrChecksum, 0x0010
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.equ MicrocodeHdrLoader, 0x0014
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.equ MicrocodeHdrFlags, 0x0018
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.equ MicrocodeHdrDataSize, 0x001C
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.equ MicrocodeHdrTotalSize, 0x0020
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.equ MicrocodeHdrRsvd, 0x0024
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MicrocodeHdrEnd:
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.equ MicrocodeHdrLength, 0x0030 # MicrocodeHdrLength = MicrocodeHdrEnd - MicrocodeHdr
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ExtSigHdr:
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.equ ExtSigHdrCount, 0x0000
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.equ ExtSigHdrChecksum, 0x0004
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.equ ExtSigHdrRsvd, 0x0008
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ExtSigHdrEnd:
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.equ ExtSigHdrLength, 0x0014 #ExtSigHdrLength = ExtSigHdrEnd - ExtSigHdr
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ExtSig:
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.equ ExtSigProcessor, 0x0000
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.equ ExtSigFlags, 0x0004
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.equ ExtSigChecksum, 0x0008
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ExtSigEnd:
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.equ ExtSigLength, 0x000C #ExtSigLength = ExtSigEnd - ExtSig
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LoadMicrocodeParams:
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.equ MicrocodeCodeAddr, 0x0000
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.equ MicrocodeCodeSize, 0x0004
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LoadMicrocodeParamsEnd:
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.macro SAVE_REGS
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pinsrw $0x00, %ebp, %xmm7
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ror $0x10, %ebp
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pinsrw $0x01, %ebp, %xmm7
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ror $0x10, %ebp
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#
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pinsrw $0x02, %ebx, %xmm7
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ror $0x10, %ebx
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pinsrw $0x03, %ebx, %xmm7
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ror $0x10, %ebx
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#
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pinsrw $0x04, %esi, %xmm7
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ror $0x10, %esi
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pinsrw $0x05, %esi, %xmm7
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ror $0x10, %esi
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#
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pinsrw $0x06, %edi, %xmm7
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ror $0x10, %edi
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pinsrw $0x07, %edi, %xmm7
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ror $0x10, %edi
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#
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pinsrw $0x00, %esp, %xmm6
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ror $0x10, %esp
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pinsrw $0x01, %esp, %xmm6
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ror $0x10, %esp
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.endm
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.macro LOAD_REGS
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pshufd $0xe4, %xmm7, %xmm7
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movd %xmm7, %ebp
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pshufd $0xe4, %xmm7, %xmm7
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#
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pshufd $0x39, %xmm7, %xmm7
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movd %xmm7, %ebx
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pshufd $0x93, %xmm7, %xmm7
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#
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pshufd $0x4e, %xmm7, %xmm7
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movd %xmm7, %esi
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pshufd $0x4e, %xmm7, %xmm7
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#
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pshufd $0x93, %xmm7, %xmm7
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movd %xmm7, %edi
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pshufd $0x39, %xmm7, %xmm7
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#
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movd %xmm6, %esp
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.endm
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.macro LOAD_EAX
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pshufd $0x39, %xmm6, %xmm6
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movd %xmm6, %eax
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pshufd $0x93, %xmm6, %xmm6
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.endm
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.macro LOAD_EDX
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pshufd $0xe4, %xmm6, %xmm6
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movd %xmm6, %edx
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pshufd $0xe4, %xmm6, %xmm6
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.endm
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.macro SAVE_EAX
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pinsrw $0x02, %eax, %xmm6
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ror $0x10, %eax
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pinsrw $0x03, %eax, %xmm6
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ror $0x10, %eax
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.endm
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.macro SAVE_EDX
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pinsrw $0x04, %edx, %xmm6
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ror $0x10, %edx
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pinsrw $0x05, %edx, %xmm6
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ror $0x10, %edx
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.endm
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.macro LOAD_ESP
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movd %xmm6, %esp
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.endm
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.macro ENABLE_SSE
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jmp NextAddress
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.align 4
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#
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# Float control word initial value:
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# all exceptions masked, double-precision, round-to-nearest
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#
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ASM_PFX(mFpuControlWord): .word 0x027F
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#
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# Multimedia-extensions control word:
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# all exceptions masked, round-to-nearest, flush to zero for masked underflow
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#
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ASM_PFX(mMmxControlWord): .long 0x01F80
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SseError:
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#
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# Processor has to support SSE
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#
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jmp SseError
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NextAddress:
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#
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# Initialize floating point units
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#
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finit
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fldcw ASM_PFX(mFpuControlWord)
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#
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# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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# whether the processor supports SSE instruction.
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#
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movl $1, %eax
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cpuid
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btl $25, %edx
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jnc SseError
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#
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# Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
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#
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movl %cr4, %eax
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orl $BIT9, %eax
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movl %eax, %cr4
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#
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# The processor should support SSE instruction and we can use
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# ldmxcsr instruction
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#
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ldmxcsr ASM_PFX(mMmxControlWord)
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.endm
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#Save in ECX-SLOT 3 in xmm6.
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.macro SAVE_EAX_MICROCODE_RET_STATUS
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pinsrw $0x6, %eax, %xmm6
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ror $0x10, %eax
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pinsrw $0x7, %eax, %xmm6
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rol $0x10, %eax
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.endm
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#Restore from ECX-SLOT 3 in xmm6.
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.macro LOAD_EAX_MICROCODE_RET_STATUS
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pshufd $0x93, %xmm6, %xmm6
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movd %xmm6, %eax
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pshufd $0x39, %xmm6, %xmm6
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.endm
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#
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# Following are fixed PCDs
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#
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ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase)
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ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize)
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ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
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#
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# Following functions will be provided in C
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#
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ASM_GLOBAL ASM_PFX(SecStartup)
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ASM_GLOBAL ASM_PFX(FspApiCallingCheck)
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#
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# Following functions will be provided in PlatformSecLib
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#
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ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddress)
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ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeader)
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ASM_GLOBAL ASM_PFX(GetBootFirmwareVolumeOffset)
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ASM_GLOBAL ASM_PFX(Loader2PeiSwitchStack)
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#
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# Define the data length that we saved on the stack top
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#
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.equ DATA_LEN_OF_PER0, 0x018
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.equ DATA_LEN_OF_MCUD, 0x018
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.equ DATA_LEN_AT_STACK_TOP, (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)
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#------------------------------------------------------------------------------
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# SecPlatformInitDefault
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# Inputs:
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# mm7 -> Return address
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# Outputs:
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# eax -> 0 - Successful, Non-zero - Failed.
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# Register Usage:
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# eax is cleared and ebp is used for return address.
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# All others reserved.
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(SecPlatformInitDefault)
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ASM_PFX(SecPlatformInitDefault):
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#
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# Save return address to EBP
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#
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movd %mm7, %ebp
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xorl %eax, %eax
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SecPlatformInitDefaultExit:
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jmp *%ebp
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#------------------------------------------------------------------------------
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# LoadMicrocodeDefault
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#
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# Inputs:
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# esp -> LoadMicrocodeParams pointer
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# Register Usage:
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# esp Preserved
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# All others destroyed
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# Assumptions:
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# No memory available, stack is hard-coded and used for return address
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# Executed by SBSP and NBSP
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# Beginning of microcode update region starts on paragraph boundary
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#------------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(LoadMicrocodeDefault)
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ASM_PFX(LoadMicrocodeDefault):
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#
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# Save return address to EBP
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#
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movd %mm7, %ebp
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cmpl $0x00, %esp
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jz ParamError
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movl 4(%esp), %eax #dword ptr [] Parameter pointer
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cmpl $0x00, %eax
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jz ParamError
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movl %eax, %esp
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movl MicrocodeCodeAddr(%esp), %esi
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cmpl $0x00, %esi
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jnz CheckMainHeader
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ParamError:
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movl $0x080000002, %eax
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jmp LoadMicrocodeExit
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CheckMainHeader:
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#
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# Get processor signature and platform ID from the installed processor
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# and save into registers for later use
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# ebx = processor signature
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# edx = platform ID
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#
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movl $0x01, %eax
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cpuid
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movl %eax, %ebx
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movl $MSR_IA32_PLATFORM_ID, %ecx
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rdmsr
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movl %edx, %ecx
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shrl $0x12, %ecx # shift (50d-32d=18d=0x12) bits
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andl $0x07, %ecx # platform id at bit[52..50]
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movl $0x01, %edx
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shll %cl,%edx
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#
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# Current register usage
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# esp -> stack with paramters
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# esi -> microcode update to check
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# ebx = processor signature
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# edx = platform ID
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#
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#
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# Check for valid microcode header
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# Minimal test checking for header version and loader version as 1
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#
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movl $0x01, %eax
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cmpl %eax, MicrocodeHdrVersion(%esi)
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jne AdvanceFixedSize
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cmpl %eax, MicrocodeHdrLoader(%esi)
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jne AdvanceFixedSize
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#
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# Check if signature and plaform ID match
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#
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cmpl MicrocodeHdrProcessor(%esi), %ebx
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jne LoadMicrocodeL0
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testl MicrocodeHdrFlags(%esi), %edx
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jnz LoadCheck #Jif signature and platform ID match
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LoadMicrocodeL0:
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#
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# Check if extended header exists
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# First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid
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#
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xorl %eax, %eax
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cmpl %eax, MicrocodeHdrTotalSize(%esi)
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je NextMicrocode
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cmpl %eax, MicrocodeHdrDataSize(%esi)
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je NextMicrocode
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#
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# Then verify total size - sizeof header > data size
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#
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movl MicrocodeHdrTotalSize(%esi), %ecx
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subl $MicrocodeHdrLength, %ecx
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cmpl MicrocodeHdrDataSize(%esi), %ecx
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jle NextMicrocode
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#
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# Set edi -> extended header
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#
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movl %esi, %edi
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addl $MicrocodeHdrLength, %edi
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addl MicrocodeHdrDataSize(%esi), %edi
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#
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# Get count of extended structures
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#
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movl ExtSigHdrCount(%edi), %ecx
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#
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# Move pointer to first signature structure
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#
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addl ExtSigHdrLength, %edi
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CheckExtSig:
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#
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# Check if extended signature and platform ID match
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#
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cmpl %ebx, ExtSigProcessor(%edi)
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jne LoadMicrocodeL1
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test %edx, ExtSigFlags(%edi)
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jnz LoadCheck # Jif signature and platform ID match
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LoadMicrocodeL1:
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#
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# Check if any more extended signatures exist
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#
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addl $ExtSigLength, %edi
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loop CheckExtSig
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NextMicrocode:
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#
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# Advance just after end of this microcode
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#
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xorl %eax, %eax
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cmpl %eax, MicrocodeHdrTotalSize(%esi)
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je LoadMicrocodeL2
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addl MicrocodeHdrTotalSize(%esi), %esi
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jmp CheckAddress
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LoadMicrocodeL2:
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addl $0x800, %esi #add esi, dword ptr 2048
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jmp CheckAddress
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AdvanceFixedSize:
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#
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# Advance by 4X dwords
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#
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addl $0x400, %esi #add esi, dword ptr 1024
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CheckAddress:
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#
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# Is valid Microcode start point ?
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#
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cmpl $0x0ffffffff, MicrocodeHdrVersion(%esi)
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#
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# Is automatic size detection ?
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#
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movl MicrocodeCodeSize(%esp), %eax
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cmpl $0x0ffffffff, %eax
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jz LoadMicrocodeL3
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#
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# Address >= microcode region address + microcode region size?
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#
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addl MicrocodeCodeAddr(%esp), %eax
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cmpl %eax, %esi
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jae Done #Jif address is outside of microcode region
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jmp CheckMainHeader
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LoadMicrocodeL3:
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LoadCheck:
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#
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# Get the revision of the current microcode update loaded
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#
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movl $MSR_IA32_BIOS_SIGN_ID, %ecx
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xorl %eax, %eax # Clear EAX
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xorl %edx, %edx # Clear EDX
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wrmsr # Load 0 to MSR at 8Bh
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movl $0x01, %eax
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cpuid
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movl $MSR_IA32_BIOS_SIGN_ID, %ecx
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rdmsr # Get current microcode signature
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#
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# Verify this microcode update is not already loaded
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#
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cmpl %edx, MicrocodeHdrRevision(%esi)
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je Continue
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LoadMicrocode0:
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#
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# EAX contains the linear address of the start of the Update Data
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# EDX contains zero
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# ECX contains 79h (IA32_BIOS_UPDT_TRIG)
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# Start microcode load with wrmsr
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#
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movl %esi, %eax
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addl $MicrocodeHdrLength, %eax
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xorl %edx, %edx
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movl $MSR_IA32_BIOS_UPDT_TRIG, %ecx
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wrmsr
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movl $0x01, %eax
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cpuid
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Continue:
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jmp NextMicrocode
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Done:
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movl $0x01, %eax
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cpuid
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movl $MSR_IA32_BIOS_SIGN_ID, %ecx
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rdmsr # Get current microcode signature
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xorl %eax, %eax
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cmpl $0x00, %edx
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jnz LoadMicrocodeExit
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movl $0x08000000E, %eax
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LoadMicrocodeExit:
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jmp *%ebp
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#----------------------------------------------------------------------------
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# EstablishStackFsp
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#
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#----------------------------------------------------------------------------
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ASM_GLOBAL ASM_PFX(EstablishStackFsp)
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ASM_PFX(EstablishStackFsp):
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#
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# Save parameter pointer in edx
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#
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movl 4(%esp), %edx
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#
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# Enable FSP STACK
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#
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movl PcdGet32(PcdTemporaryRamBase), %esp
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addl PcdGet32(PcdTemporaryRamSize), %esp
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pushl $DATA_LEN_OF_MCUD # Size of the data region
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pushl $0x4455434D # Signature of the data region 'MCUD'
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pushl 12(%edx) # Code size
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pushl 8(%edx) # Code base
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pushl 4(%edx) # Microcode size
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pushl (%edx) # Microcode base
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#
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# Save API entry/exit timestamp into stack
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#
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pushl $DATA_LEN_OF_PER0 # Size of the data region
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pushl $0x30524550 # Signature of the data region 'PER0'
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LOAD_EDX
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pushl %edx
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LOAD_EAX
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pushl %eax
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rdtsc
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pushl %edx
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pushl %eax
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#
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# Terminator for the data on stack
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#
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push $0x00
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#
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# Set ECX/EDX to the BootLoader temporary memory range
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#
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movl PcdGet32 (PcdTemporaryRamBase), %ecx
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movl %ecx, %edx
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addl PcdGet32 (PcdTemporaryRamSize), %edx
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subl PcdGet32 (PcdFspTemporaryRamSize), %edx
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xorl %eax, %eax
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movd %mm7, %esi #RET_ESI
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jmp *%esi
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#----------------------------------------------------------------------------
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# TempRamInit API
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#
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# This FSP API will load the microcode update, enable code caching for the
|
|
# region specified by the boot loader and also setup a temporary stack to be
|
|
# used till main memory is initialized.
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(TempRamInitApi)
|
|
ASM_PFX(TempRamInitApi):
|
|
#
|
|
# Ensure SSE is enabled
|
|
#
|
|
ENABLE_SSE
|
|
|
|
#
|
|
# Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6
|
|
#
|
|
SAVE_REGS
|
|
|
|
#
|
|
# Save timestamp into XMM6
|
|
#
|
|
rdtsc
|
|
SAVE_EAX
|
|
SAVE_EDX
|
|
|
|
#
|
|
# Check Parameter
|
|
#
|
|
movl 4(%esp), %eax
|
|
cmpl $0x00, %eax
|
|
movl $0x80000002, %eax
|
|
jz NemInitExit
|
|
|
|
#
|
|
# Sec Platform Init
|
|
#
|
|
movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit
|
|
movd %esi, %mm7
|
|
.weak ASM_PFX(SecPlatformInit)
|
|
.set ASM_PFX(SecPlatformInit), ASM_PFX(SecPlatformInitDefault)
|
|
jmp ASM_PFX(SecPlatformInit)
|
|
TempRamInitApiL1:
|
|
cmpl $0x00, %eax
|
|
jnz NemInitExit
|
|
|
|
#
|
|
# Load microcode
|
|
#
|
|
LOAD_ESP
|
|
movl $TempRamInitApiL2, %esi #CALL_MMX LoadMicrocode
|
|
movd %esi, %mm7
|
|
.weak ASM_PFX(LoadMicrocode)
|
|
.set ASM_PFX(LoadMicrocode), ASM_PFX(LoadMicrocodeDefault)
|
|
jmp ASM_PFX(LoadMicrocode)
|
|
TempRamInitApiL2:
|
|
SAVE_EAX_MICROCODE_RET_STATUS #Save microcode return status in ECX-SLOT 3 in xmm6.
|
|
#@note If return value eax is not 0, microcode did not load, but continue and attempt to boot from ECX-SLOT 3 in xmm6.
|
|
|
|
#
|
|
# Call Sec CAR Init
|
|
#
|
|
LOAD_ESP
|
|
movl $TempRamInitApiL3, %esi #CALL_MMX SecCarInit
|
|
movd %esi, %mm7
|
|
jmp ASM_PFX(SecCarInit)
|
|
TempRamInitApiL3:
|
|
cmpl $0x00, %eax
|
|
jnz NemInitExit
|
|
|
|
#
|
|
# EstablishStackFsp
|
|
#
|
|
LOAD_ESP
|
|
movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp
|
|
movd %esi, %mm7
|
|
jmp ASM_PFX(EstablishStackFsp)
|
|
TempRamInitApiL4:
|
|
|
|
LOAD_EAX_MICROCODE_RET_STATUS #Restore microcode status if no CAR init error.
|
|
|
|
NemInitExit:
|
|
#
|
|
# Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6
|
|
#
|
|
LOAD_REGS
|
|
ret
|
|
|
|
|
|
#----------------------------------------------------------------------------
|
|
# FspInit API
|
|
#
|
|
# This FSP API will perform the processor and chipset initialization.
|
|
# This API will not return. Instead, it transfers the control to the
|
|
# ContinuationFunc provided in the parameter.
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(FspInitApi)
|
|
ASM_PFX(FspInitApi):
|
|
movl $0x01, %eax
|
|
jmp FspApiCommon
|
|
|
|
#----------------------------------------------------------------------------
|
|
# NotifyPhase API
|
|
#
|
|
# This FSP API will notify the FSP about the different phases in the boot
|
|
# process
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(NotifyPhaseApi)
|
|
ASM_PFX(NotifyPhaseApi):
|
|
movl $0x02, %eax
|
|
jmp FspApiCommon
|
|
|
|
#----------------------------------------------------------------------------
|
|
# FspMemoryInit API
|
|
#
|
|
# This FSP API is called after TempRamInit and initializes the memory.
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(FspMemoryInitApi)
|
|
ASM_PFX(FspMemoryInitApi):
|
|
movl $0x03, %eax
|
|
jmp FspApiCommon
|
|
|
|
#----------------------------------------------------------------------------
|
|
# TempRamExitApi API
|
|
#
|
|
# This API tears down temporary RAM
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(TempRamExitApi)
|
|
ASM_PFX(TempRamExitApi):
|
|
movl $0x04, %eax
|
|
jmp FspApiCommon
|
|
|
|
#----------------------------------------------------------------------------
|
|
# FspSiliconInit API
|
|
#
|
|
# This FSP API initializes the CPU and the chipset including the IO
|
|
# controllers in the chipset to enable normal operation of these devices.
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(FspSiliconInitApi)
|
|
ASM_PFX(FspSiliconInitApi):
|
|
movl $0x05, %eax
|
|
jmp FspApiCommon
|
|
|
|
#----------------------------------------------------------------------------
|
|
# FspApiCommon API
|
|
#
|
|
# This is the FSP API common entry point to resume the FSP execution
|
|
#
|
|
#----------------------------------------------------------------------------
|
|
ASM_GLOBAL ASM_PFX(FspApiCommon)
|
|
ASM_PFX(FspApiCommon):
|
|
#
|
|
# EAX holds the API index
|
|
#
|
|
|
|
#
|
|
# Stack must be ready
|
|
#
|
|
pushl %eax
|
|
addl $0x04, %esp
|
|
cmpl -4(%esp), %eax
|
|
jz FspApiCommonL0
|
|
movl $0x080000003, %eax
|
|
jmp FspApiCommonExit
|
|
|
|
FspApiCommonL0:
|
|
#
|
|
# Verify the calling condition
|
|
#
|
|
pushal
|
|
pushl 36(%esp) #push ApiParam [esp + 4 * 8 + 4]
|
|
pushl %eax #push ApiIdx
|
|
call ASM_PFX(FspApiCallingCheck)
|
|
addl $0x08, %esp
|
|
cmpl $0x00, %eax
|
|
jz FspApiCommonL1
|
|
movl %eax, 0x1C(%esp) # mov dword ptr [esp + 4 * 7], eax
|
|
popal
|
|
ret
|
|
|
|
FspApiCommonL1:
|
|
popal
|
|
cmpl $0x01, %eax # FspInit API
|
|
jz FspApiCommonL2
|
|
cmpl $0x03, %eax # FspMemoryInit API
|
|
jz FspApiCommonL2
|
|
call ASM_PFX(AsmGetFspInfoHeader)
|
|
jmp Loader2PeiSwitchStack
|
|
|
|
FspApiCommonL2:
|
|
#
|
|
# FspInit and FspMemoryInit APIs, setup the initial stack frame
|
|
#
|
|
|
|
#
|
|
# Place holder to store the FspInfoHeader pointer
|
|
#
|
|
pushl %eax
|
|
|
|
#
|
|
# Update the FspInfoHeader pointer
|
|
#
|
|
pushl %eax
|
|
call ASM_PFX(AsmGetFspInfoHeader)
|
|
movl %eax, 4(%esp)
|
|
popl %eax
|
|
|
|
#
|
|
# Create a Task Frame in the stack for the Boot Loader
|
|
#
|
|
pushfl # 2 pushf for 4 byte alignment
|
|
cli
|
|
pushal
|
|
|
|
#
|
|
# Reserve 8 bytes for IDT save/restore
|
|
#
|
|
subl $0x08, %esp
|
|
sidt (%esp)
|
|
|
|
#
|
|
# Setup new FSP stack
|
|
#
|
|
movl %esp, %edi
|
|
movl PcdGet32(PcdTemporaryRamBase), %esp
|
|
addl PcdGet32(PcdTemporaryRamSize), %esp
|
|
subl $(DATA_LEN_AT_STACK_TOP + 0x40), %esp
|
|
|
|
#
|
|
# Pass the API Idx to SecStartup
|
|
#
|
|
pushl %eax
|
|
|
|
#
|
|
# Pass the BootLoader stack to SecStartup
|
|
#
|
|
pushl %edi
|
|
|
|
#
|
|
# Pass entry point of the PEI core
|
|
#
|
|
call ASM_PFX(AsmGetFspBaseAddress)
|
|
movl %eax, %edi
|
|
addl PcdGet32(PcdFspAreaSize), %edi
|
|
subl $0x20, %edi
|
|
addl %ds:(%edi), %eax
|
|
pushl %eax
|
|
|
|
#
|
|
# Pass BFV into the PEI Core
|
|
# It uses relative address to calucate the actual boot FV base
|
|
# For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
|
|
# PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
|
|
# they are different. The code below can handle both cases.
|
|
#
|
|
call ASM_PFX(AsmGetFspBaseAddress)
|
|
movl %eax, %edi
|
|
call ASM_PFX(GetBootFirmwareVolumeOffset)
|
|
addl %edi, %eax
|
|
pushl %eax
|
|
|
|
#
|
|
# Pass stack base and size into the PEI Core
|
|
#
|
|
movl PcdGet32(PcdTemporaryRamBase), %eax
|
|
addl PcdGet32(PcdTemporaryRamSize), %eax
|
|
subl PcdGet32(PcdFspTemporaryRamSize), %eax
|
|
pushl %eax
|
|
pushl PcdGet32(PcdFspTemporaryRamSize)
|
|
|
|
#
|
|
# Pass Control into the PEI Core
|
|
#
|
|
call ASM_PFX(SecStartup)
|
|
addl $4, %esp
|
|
FspApiCommonExit:
|
|
ret
|
|
|