9da591867c
-- Add BootLoaderTolumSize support -- Extend FspApiCallingCheck with ApiParam for BootLoaderTolumSize -- Rename all Bootloader to BootLoader as official name -- Rename Ucode to Microcode -- Remove FspSelfCheck API, because it is merged into SecPlatformInit -- Add GetFspVpdDataPointer() in FspCommonLib.h -- Document FspSecPlatformLib.h -- Reorg FSP_PLAT_DATA data structure to let it match FSP spec. -- Move helper function in FspSecCore to reduce platform enabling effort -- Fix LibraryClasses declaration in DEC file. -- Enhance PatchFv to check if it is valid FSP bin. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17196 6f19259b-4bc3-4df7-8a09-765794883524
185 lines
4.7 KiB
PHP
185 lines
4.7 KiB
PHP
;------------------------------------------------------------------------------
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;
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; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Abstract:
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;
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; Provide macro for register save/restore using SSE registers
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;
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;------------------------------------------------------------------------------
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;
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; Define SSE instruction set
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;
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IFDEF USE_SSE41_FLAG
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;
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; Define SSE macros using SSE 4.1 instructions
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;
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SXMMN MACRO XMM, IDX, REG
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pinsrd XMM, REG, (IDX AND 3)
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ENDM
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LXMMN MACRO XMM, REG, IDX
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pextrd REG, XMM, (IDX AND 3)
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ENDM
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ELSE
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;
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; Define SSE macros using SSE 2 instructions
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;
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SXMMN MACRO XMM, IDX, REG
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pinsrw XMM, REG, (IDX AND 3) * 2
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ror REG, 16
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pinsrw XMM, REG, (IDX AND 3) * 2 + 1
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rol REG, 16
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ENDM
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LXMMN MACRO XMM, REG, IDX
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pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2)) AND 0FFh
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movd REG, XMM
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pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh
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ENDM
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ENDIF
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;
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; XMM7 to save/restore EBP, EBX, ESI, EDI
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;
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SAVE_REGS MACRO
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SXMMN xmm7, 0, ebp
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SXMMN xmm7, 1, ebx
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SXMMN xmm7, 2, esi
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SXMMN xmm7, 3, edi
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SAVE_ESP
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ENDM
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LOAD_REGS MACRO
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LXMMN xmm7, ebp, 0
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LXMMN xmm7, ebx, 1
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LXMMN xmm7, esi, 2
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LXMMN xmm7, edi, 3
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LOAD_ESP
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ENDM
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;
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; XMM6 to save/restore EAX, EDX, ECX, ESP
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;
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LOAD_EAX MACRO
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LXMMN xmm6, eax, 1
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ENDM
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SAVE_EAX MACRO
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SXMMN xmm6, 1, eax
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ENDM
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LOAD_EDX MACRO
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LXMMN xmm6, edx, 2
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ENDM
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SAVE_EDX MACRO
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SXMMN xmm6, 2, edx
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ENDM
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SAVE_ECX MACRO
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SXMMN xmm6, 3, ecx
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ENDM
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LOAD_ECX MACRO
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LXMMN xmm6, ecx, 3
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ENDM
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SAVE_ESP MACRO
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SXMMN xmm6, 0, esp
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ENDM
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LOAD_ESP MACRO
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movd esp, xmm6
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ENDM
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;
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; XMM5 for calling stack
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;
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CALL_XMM MACRO Entry
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local ReturnAddress
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mov esi, offset ReturnAddress
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pslldq xmm5, 4
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IFDEF USE_SSE41_FLAG
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pinsrd xmm5, esi, 0
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ELSE
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pinsrw xmm5, esi, 0
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ror esi, 16
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pinsrw xmm5, esi, 1
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ENDIF
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mov esi, Entry
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jmp esi
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ReturnAddress:
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ENDM
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RET_XMM MACRO
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movd esi, xmm5
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psrldq xmm5, 4
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jmp esi
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ENDM
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ENABLE_SSE MACRO
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;
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; Initialize floating point units
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;
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local NextAddress
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jmp NextAddress
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ALIGN 4
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;
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; Float control word initial value:
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; all exceptions masked, double-precision, round-to-nearest
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;
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FpuControlWord DW 027Fh
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;
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; Multimedia-extensions control word:
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; all exceptions masked, round-to-nearest, flush to zero for masked underflow
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;
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MmxControlWord DD 01F80h
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SseError:
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;
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; Processor has to support SSE
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;
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jmp SseError
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NextAddress:
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finit
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fldcw FpuControlWord
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;
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; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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; whether the processor supports SSE instruction.
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;
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mov eax, 1
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cpuid
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bt edx, 25
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jnc SseError
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IFDEF USE_SSE41_FLAG
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;
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; SSE 4.1 support
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;
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bt ecx, 19
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jnc SseError
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ENDIF
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;
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; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
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;
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mov eax, cr4
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or eax, 00000600h
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mov cr4, eax
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;
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; The processor should support SSE instruction and we can use
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; ldmxcsr instruction
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;
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ldmxcsr MmxControlWord
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ENDM
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