b1b69d2606
There is no functional modification in this change As preparation for further work, the formatting is corrected to meet the EDKII coding standard. Of specific note, some invalid include guards were fixed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
141 lines
3.9 KiB
C
141 lines
3.9 KiB
C
/** @file
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Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/LcdHwLib.h>
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#include <Library/LcdPlatformLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include "PL111Lcd.h"
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/** This file contains all the bits of the PL111 that are
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platform independent.
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**/
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EFI_STATUS
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LcdIdentify (
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VOID
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)
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{
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DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n",
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PL111_REG_CLCD_PERIPH_ID_0));
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// Check if this is a PL111
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if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 &&
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MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 &&
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(MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 &&
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MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 &&
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MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 &&
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MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 &&
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MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 &&
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MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) {
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return EFI_SUCCESS;
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}
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return EFI_NOT_FOUND;
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}
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EFI_STATUS
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LcdInitialize (
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IN EFI_PHYSICAL_ADDRESS VramBaseAddress
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)
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{
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// Define start of the VRAM. This never changes for any graphics mode
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MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress);
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MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
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// Disable all interrupts from the PL111
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MmioWrite32 (PL111_REG_LCD_IMSC, 0);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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LcdSetMode (
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IN UINT32 ModeNumber
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)
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{
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EFI_STATUS Status;
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UINT32 HRes;
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UINT32 HSync;
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UINT32 HBackPorch;
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UINT32 HFrontPorch;
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UINT32 VRes;
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UINT32 VSync;
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UINT32 VBackPorch;
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UINT32 VFrontPorch;
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UINT32 LcdControl;
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LCD_BPP LcdBpp;
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// Set the video mode timings and other relevant information
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Status = LcdPlatformGetTimings (
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ModeNumber,
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&HRes,
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&HSync,
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&HBackPorch,
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&HFrontPorch,
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&VRes,
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&VSync,
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&VBackPorch,
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&VFrontPorch
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);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return EFI_DEVICE_ERROR;
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}
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Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR (Status)) {
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return EFI_DEVICE_ERROR;
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}
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// Disable the CLCD_LcdEn bit
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LcdControl = MmioRead32 (PL111_REG_LCD_CONTROL);
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MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1);
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// Set Timings
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MmioWrite32 (
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PL111_REG_LCD_TIMING_0,
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HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes)
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);
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MmioWrite32 (
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PL111_REG_LCD_TIMING_1,
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VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes)
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);
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MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes));
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MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);
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// PL111_REG_LCD_CONTROL
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LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) |
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PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;
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MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
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// Turn on power to the LCD Panel
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LcdControl |= PL111_CTRL_LCD_PWR;
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MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl);
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return EFI_SUCCESS;
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}
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VOID
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LcdShutdown (
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VOID
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)
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{
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// Disable the controller
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MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);
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}
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