b20085454e
GCC8 reported it with the following warning:
ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c: In function 'DisassembleArmInstruction':
ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c:397:30: error: bitwise
comparison always evaluates to false [-Werror=tautological-compare]
if ((OpCode & 0x0db00000) == 0x03200000) {
This condition tries to be true for both the immediate and the register
version of the MSR instruction. They get identified inside the if-block
using the variable I, which contains the value of bit 25.
The problem with the comparison reported by GCC is that the
bitmask excludes bit 25, while the value requires it to be set to one:
0x0db00000: 0000 11011 0 11 00 00 0000 000000000000
0x03200000: 0000 00110 0 10 00 00 0000 000000000000
^
So the solution is to just don't require that bit to be set, because
it gets checked later using 'I', which results in the following value:
0x01200000: 0000 00010 0 10 00 00 0000 000000000000
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
456 lines
14 KiB
C
456 lines
14 KiB
C
/** @file
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Default exception handler
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/PrintLib.h>
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#include <Library/ArmDisassemblerLib.h>
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CHAR8 *gCondition[] = {
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"EQ",
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"NE",
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"CS",
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"CC",
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"MI",
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"PL",
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"VS",
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"VC",
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"HI",
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"LS",
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"GE",
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"LT",
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"GT",
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"LE",
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"",
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"2"
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};
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#define COND(_a) gCondition[((_a) >> 28)]
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CHAR8 *gReg[] = {
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"r0",
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"r1",
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"r2",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"sp",
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"lr",
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"pc"
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};
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CHAR8 *gLdmAdr[] = {
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"DA",
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"IA",
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"DB",
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"IB"
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};
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CHAR8 *gLdmStack[] = {
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"FA",
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"FD",
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"EA",
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"ED"
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};
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#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
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#define SIGN(_U) ((_U) ? "" : "-")
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#define WRITE(_W) ((_W) ? "!" : "")
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#define BYTE(_B) ((_B) ? "B":"")
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#define USER(_B) ((_B) ? "^" : "")
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CHAR8 mMregListStr[4*15 + 1];
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CHAR8 *
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MRegList (
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UINT32 OpCode
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)
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{
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UINTN Index, Start, End;
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BOOLEAN First;
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mMregListStr[0] = '\0';
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");
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for (Index = 0, First = TRUE; Index <= 15; Index++) {
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if ((OpCode & (1 << Index)) != 0) {
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Start = End = Index;
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for (Index++; ((OpCode & (1 << Index)) != 0) && Index <= 15; Index++) {
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End = Index;
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}
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if (!First) {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, ",");
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} else {
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First = FALSE;
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}
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if (Start == End) {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]);
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, ", ");
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} else {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[Start]);
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "-");
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, gReg[End]);
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}
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}
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}
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if (First) {
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");
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}
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AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");
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// BugBug: Make caller pass in buffer it is cleaner
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return mMregListStr;
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}
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CHAR8 *
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FieldMask (
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IN UINT32 Mask
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)
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{
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return "";
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}
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UINT32
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RotateRight (
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IN UINT32 Op,
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IN UINT32 Shift
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)
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{
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return (Op >> Shift) | (Op << (32 - Shift));
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}
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/**
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Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instructin.
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We cheat and only decode instructions that access
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memory. If the instruction is not found we dump the instruction in hex.
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@param OpCodePtr Pointer to pointer of ARM instruction to disassemble.
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@param Buf Buffer to sprintf disassembly into.
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@param Size Size of Buf in bytes.
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@param Extended TRUE dump hex for instruction too.
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**/
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VOID
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DisassembleArmInstruction (
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IN UINT32 **OpCodePtr,
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OUT CHAR8 *Buf,
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OUT UINTN Size,
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IN BOOLEAN Extended
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)
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{
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UINT32 OpCode = **OpCodePtr;
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CHAR8 *Type, *Root;
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BOOLEAN I, P, U, B, W, L, S, H;
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UINT32 Rn, Rd, Rm;
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UINT32 imode, offset_8, offset_12;
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UINT32 Index;
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UINT32 shift_imm, shift;
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I = (OpCode & BIT25) == BIT25;
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P = (OpCode & BIT24) == BIT24;
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U = (OpCode & BIT23) == BIT23;
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B = (OpCode & BIT22) == BIT22; // Also called S
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W = (OpCode & BIT21) == BIT21;
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L = (OpCode & BIT20) == BIT20;
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S = (OpCode & BIT6) == BIT6;
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H = (OpCode & BIT5) == BIT5;
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Rn = (OpCode >> 16) & 0xf;
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Rd = (OpCode >> 12) & 0xf;
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Rm = (OpCode & 0xf);
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if (Extended) {
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Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode);
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Buf += Index;
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Size -= Index;
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}
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// LDREX, STREX
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if ((OpCode & 0x0fe000f0) == 0x01800090) {
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if (L) {
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// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
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AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
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} else {
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// A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
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AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
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}
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return;
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}
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// LDM/STM
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if ((OpCode & 0x0e000000) == 0x08000000) {
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if (L) {
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// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
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// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
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// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
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AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
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} else {
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// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
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// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
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AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
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}
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return;
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}
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// LDR/STR Address Mode 2
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if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
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offset_12 = OpCode & 0xfff;
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if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
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Index = AsciiSPrint (Buf, Size, "PLD");
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} else {
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Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
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}
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if (P) {
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if (!I) {
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// A5.2.2 [<Rn>, #+/-<offset_12>]
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// A5.2.5 [<Rn>, #+/-<offset_12>]
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W));
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} else if ((OpCode & 0x03000ff0) == 0x03000000) {
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// A5.2.3 [<Rn>, +/-<Rm>]
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// A5.2.6 [<Rn>, +/-<Rm>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W));
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} else {
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// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
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// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
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shift_imm = (OpCode >> 7) & 0x1f;
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shift = (OpCode >> 5) & 0x3;
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if (shift == 0x0) {
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Type = "LSL";
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} else if (shift == 0x1) {
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Type = "LSR";
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if (shift_imm == 0) {
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shift_imm = 32;
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}
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} else if (shift == 0x12) {
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Type = "ASR";
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} else if (shift_imm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
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return;
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} else {
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Type = "ROR";
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}
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
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}
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} else { // !P
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if (!I) {
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// A5.2.8 [<Rn>], #+/-<offset_12>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12);
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} else if ((OpCode & 0x03000ff0) == 0x03000000) {
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// A5.2.9 [<Rn>], +/-<Rm>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
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} else {
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// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
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shift_imm = (OpCode >> 7) & 0x1f;
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shift = (OpCode >> 5) & 0x3;
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if (shift == 0x0) {
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Type = "LSL";
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} else if (shift == 0x1) {
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Type = "LSR";
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if (shift_imm == 0) {
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shift_imm = 32;
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}
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} else if (shift == 0x12) {
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Type = "ASR";
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} else if (shift_imm == 0) {
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);
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// FIx me
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return;
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} else {
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Type = "ROR";
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}
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);
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}
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}
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return;
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}
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if ((OpCode & 0x0e000000) == 0x00000000) {
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// LDR/STR address mode 3
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// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
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if (L) {
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if (!S) {
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Root = "LDR%aH %a, ";
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} else if (!H) {
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Root = "LDR%aSB %a, ";
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} else {
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Root = "LDR%aSH %a, ";
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}
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} else {
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if (!S) {
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Root = "STR%aH %a ";
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} else if (!H) {
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Root = "LDR%aD %a ";
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} else {
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Root = "STR%aD %a ";
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}
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}
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Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
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S = (OpCode & BIT6) == BIT6;
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H = (OpCode & BIT5) == BIT5;
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offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
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if (P & !W) {
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// Immediate offset/index
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if (B) {
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// A5.3.2 [<Rn>, #+/-<offset_8>]
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// A5.3.4 [<Rn>, #+/-<offset_8>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W));
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} else {
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// A5.3.3 [<Rn>, +/-<Rm>]
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// A5.3.5 [<Rn>, +/-<Rm>]!
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AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
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}
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} else {
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// Register offset/index
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if (B) {
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// A5.3.6 [<Rn>], #+/-<offset_8>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8);
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} else {
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// A5.3.7 [<Rn>], +/-<Rm>
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AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
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}
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}
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return;
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}
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if ((OpCode & 0x0fb000f0) == 0x01000050) {
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// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
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// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
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AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);
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return;
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}
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if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
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// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
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AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));
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return;
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}
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if ((OpCode & 0xfe500f00) == 0xf8100500) {
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// A4.1.59 RFE<addressing_mode> <Rn>{!}
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AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));
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return;
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}
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if ((OpCode & 0xfff000f0) == 0xe1200070) {
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// A4.1.7 BKPT <immed_16>
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AsciiSPrint (Buf, Size, "BKPT %x", ((OpCode >> 8) | (OpCode & 0xf)) & 0xffff);
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return;
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}
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if ((OpCode & 0xfff10020) == 0xf1000000) {
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// A4.1.16 CPS<effect> <iflags> {, #<mode>}
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if (((OpCode >> 6) & 0x7) == 0) {
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AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
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} else {
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imode = (OpCode >> 18) & 0x3;
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Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", (imode == 3) ? "ID":"IE", (OpCode & BIT8) ? "A":"", (OpCode & BIT7) ? "I":"", (OpCode & BIT6) ? "F":"");
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if ((OpCode & BIT17) != 0) {
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AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
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}
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}
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return;
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}
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if ((OpCode & 0x0f000000) == 0x0f000000) {
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// A4.1.107 SWI{<cond>} <immed_24>
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AsciiSPrint (Buf, Size, "SWI%a %x", COND (OpCode), OpCode & 0x00ffffff);
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return;
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}
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if ((OpCode & 0x0fb00000) == 0x01000000) {
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// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
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AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");
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return;
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}
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if ((OpCode & 0x0db00000) == 0x01200000) {
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// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
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if (I) {
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// MSR{<cond>} CPSR_<fields>, #<immediate>
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AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
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} else {
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// MSR{<cond>} CPSR_<fields>, <Rm>
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AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);
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}
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return;
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}
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if ((OpCode & 0xff000010) == 0xfe000000) {
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// A4.1.13 CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
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AsciiSPrint (Buf, Size, "CDP%a 0x%x, 0x%x, CR%d, CR%d, CR%d, 0x%x", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, Rn, Rd, Rm, (OpCode >> 5) &0x7);
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return;
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}
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if ((OpCode & 0x0e000000) == 0x0c000000) {
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// A4.1.19 LDC and A4.1.96 SDC
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if ((OpCode & 0xf0000000) == 0xf0000000) {
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|
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
|
|
} else {
|
|
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
|
|
}
|
|
|
|
if (!P) {
|
|
if (!W) {
|
|
// A5.5.5.5 [<Rn>], <option>
|
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
|
|
} else {
|
|
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
|
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);
|
|
}
|
|
} else {
|
|
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
|
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));
|
|
}
|
|
|
|
}
|
|
|
|
if ((OpCode & 0x0f000010) == 0x0e000010) {
|
|
// A4.1.32 MRC2, MCR2
|
|
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
|
|
return;
|
|
}
|
|
|
|
if ((OpCode & 0x0ff00000) == 0x0c400000) {
|
|
// A4.1.33 MRRC2, MCRR2
|
|
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
|
|
return;
|
|
}
|
|
|
|
AsciiSPrint (Buf, Size, "Faulting OpCode 0x%08x", OpCode);
|
|
|
|
*OpCodePtr += 1;
|
|
return;
|
|
}
|
|
|