4059386c70
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
83 lines
1.9 KiB
NASM
83 lines
1.9 KiB
NASM
//
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// Copyright (c) 2014, ARM Limited. All rights reserved.
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//
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// For the moment we assume this will run in SVC mode on ARMv7
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INCLUDE AsmMacroExport.inc
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//UINT32
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//EFIAPI
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//ArmGicGetControlSystemRegisterEnable (
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// VOID
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// );
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RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable
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mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
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bx lr
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//VOID
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//EFIAPI
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//ArmGicSetControlSystemRegisterEnable (
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// IN UINT32 ControlSystemRegisterEnable
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// );
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RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable
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mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
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isb
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bx lr
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//VOID
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//ArmGicV3EnableInterruptInterface (
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// VOID
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// );
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RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface
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mov r0, #1
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mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
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bx lr
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//VOID
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//ArmGicV3DisableInterruptInterface (
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// VOID
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// );
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RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface
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mov r0, #0
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mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
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bx lr
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//VOID
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//ArmGicV3EndOfInterrupt (
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// IN UINTN InterruptId
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// );
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RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt
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mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
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bx lr
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//UINTN
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//ArmGicV3AcknowledgeInterrupt (
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// VOID
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// );
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RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt
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mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1
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bx lr
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//VOID
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//ArmGicV3SetPriorityMask (
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// IN UINTN Priority
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// );
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RVCT_ASM_EXPORT ArmGicV3SetPriorityMask
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mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
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bx lr
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//VOID
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//ArmGicV3SetBinaryPointer (
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// IN UINTN BinaryPoint
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// );
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RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer
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mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
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bx lr
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END
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