6b46d77243
Management Mode (MM) is a generic term used to describe a secure execution environment provided by the CPU and related silicon that is entered when the CPU detects a MMI. For x86 systems, this can be implemented with System Management Mode (SMM). For ARM systems, this can be implemented with TrustZone (TZ). A MMI can be a CPU instruction or interrupt. Upon detection of a MMI, a CPU will jump to the MM Entry Point and save some portion of its state (the "save state") such that execution can be resumed. The MMI can be generated synchronously by software or asynchronously by a hardware event. Each MMI source can be detected, cleared and disabled. Some systems provide for special memory (Management Mode RAM or MMRAM) which is set aside for software running in MM. Usually the MMRAM is hidden during normal CPU execution, but this is not required. Usually, after MMRAM is hidden it cannot be exposed until the next system reset. The MM Core Interface Specification describes three pieces of the PI Management Mode architecture: 1. MM Dispatch During DXE, the DXE Foundation works with the MM Foundation to schedule MM drivers for execution in the discovered firmware volumes. 2. MM Initialization MM related code opens MMRAM, creates the MMRAM memory map, and launches the MM Foundation, which provides the necessary services to launch MM-related drivers. Then, sometime before boot, MMRAM is closed and locked. This piece may be completed during the SEC, PEI or DXE phases. 3. MMI Management When an MMI generated, the MM environment is created and then the MMI sources are detected and MMI handlers called. This patch implements the MM Core. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/** @file
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The internal header file that declared a data structure that is shared
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between the MM IPL and the MM Core.
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Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _STANDALONE_MM_CORE_PRIVATE_DATA_H_
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#define _STANDALONE_MM_CORE_PRIVATE_DATA_H_
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#include <Guid/MmCoreData.h>
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//
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// Page management
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//
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typedef struct {
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LIST_ENTRY Link;
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UINTN NumberOfPages;
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} FREE_PAGE_LIST;
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extern LIST_ENTRY mMmMemoryMap;
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//
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// Pool management
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//
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//
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// MIN_POOL_SHIFT must not be less than 5
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//
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#define MIN_POOL_SHIFT 6
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#define MIN_POOL_SIZE (1 << MIN_POOL_SHIFT)
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//
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// MAX_POOL_SHIFT must not be less than EFI_PAGE_SHIFT - 1
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//
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#define MAX_POOL_SHIFT (EFI_PAGE_SHIFT - 1)
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#define MAX_POOL_SIZE (1 << MAX_POOL_SHIFT)
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//
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// MAX_POOL_INDEX are calculated by maximum and minimum pool sizes
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//
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#define MAX_POOL_INDEX (MAX_POOL_SHIFT - MIN_POOL_SHIFT + 1)
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typedef struct {
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UINTN Size;
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BOOLEAN Available;
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} POOL_HEADER;
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typedef struct {
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POOL_HEADER Header;
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LIST_ENTRY Link;
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} FREE_POOL_HEADER;
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extern LIST_ENTRY mMmPoolLists[MAX_POOL_INDEX];
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#endif
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