0803854bc1
PI 1.2 SMM Drivers are allowed to call UEFI/DXE services and Protocols from the entry point of the PI 1.2 SMM Driver. These UEFI/DXE services and Protocols may directly or indirectly calls the UEFI Boot Services RaiseTPL() and RestoreTPL(). These UEFI Boot Services use the CPU Architectural Protocol to enable interrupts if the TPL level is below TPL_HIGH_LEVEL and enable interrupts of the TPL is at TPL_HIGH_LEVEL. Interrupts should be masked while executing SMM drivers, so if a direct or indirect call to the UEFI Boot Service RestoreTPL() would enable interrupts, then an interrupt could be incorrectly delivered in SMM context. The solution is for the DXE Core to register for the PI 1.2 SMM Base2 Protocol. If that protocol is present in the platform, then the DXE Core can use the SMM Base 2 Protocol's InSmm() function to determine if the platform is currently executing in SMM content. If the current context is in SMM, then do not allow any requests to be forwarded to the CPU Architecture Protocol to enable interrupts. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9997 6f19259b-4bc3-4df7-8a09-765794883524
143 lines
2.8 KiB
C
143 lines
2.8 KiB
C
/** @file
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Task priority (TPL) functions.
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Copyright (c) 2006 - 2010, Intel Corporation. <BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DxeMain.h"
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#include "Event.h"
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/**
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Set Interrupt State.
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@param Enable The state of enable or disable interrupt
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**/
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VOID
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CoreSetInterruptState (
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IN BOOLEAN Enable
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)
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{
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EFI_STATUS Status;
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BOOLEAN InSmm;
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if (gCpu == NULL) {
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return;
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}
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if (!Enable) {
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gCpu->DisableInterrupt (gCpu);
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return;
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}
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if (gSmmBase2 == NULL) {
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gCpu->EnableInterrupt (gCpu);
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return;
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}
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Status = gSmmBase2->InSmm (gSmmBase2, &InSmm);
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if (!EFI_ERROR (Status) && !InSmm) {
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gCpu->EnableInterrupt(gCpu);
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}
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}
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/**
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Raise the task priority level to the new level.
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High level is implemented by disabling processor interrupts.
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@param NewTpl New task priority level
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@return The previous task priority level
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**/
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EFI_TPL
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EFIAPI
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CoreRaiseTpl (
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IN EFI_TPL NewTpl
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)
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{
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EFI_TPL OldTpl;
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OldTpl = gEfiCurrentTpl;
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ASSERT (OldTpl <= NewTpl);
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ASSERT (VALID_TPL (NewTpl));
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//
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// If raising to high level, disable interrupts
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//
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if (NewTpl >= TPL_HIGH_LEVEL && OldTpl < TPL_HIGH_LEVEL) {
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CoreSetInterruptState (FALSE);
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}
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//
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// Set the new value
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//
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gEfiCurrentTpl = NewTpl;
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return OldTpl;
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}
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/**
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Lowers the task priority to the previous value. If the new
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priority unmasks events at a higher priority, they are dispatched.
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@param NewTpl New, lower, task priority
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**/
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VOID
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EFIAPI
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CoreRestoreTpl (
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IN EFI_TPL NewTpl
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)
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{
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EFI_TPL OldTpl;
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OldTpl = gEfiCurrentTpl;
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ASSERT (NewTpl <= OldTpl);
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ASSERT (VALID_TPL (NewTpl));
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//
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// If lowering below HIGH_LEVEL, make sure
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// interrupts are enabled
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//
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if (OldTpl >= TPL_HIGH_LEVEL && NewTpl < TPL_HIGH_LEVEL) {
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gEfiCurrentTpl = TPL_HIGH_LEVEL;
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}
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//
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// Dispatch any pending events
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//
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while (((-2 << NewTpl) & gEventPending) != 0) {
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gEfiCurrentTpl = HighBitSet64 (gEventPending);
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if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {
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CoreSetInterruptState (TRUE);
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}
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CoreDispatchEventNotifies (gEfiCurrentTpl);
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}
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//
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// Set the new value
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//
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gEfiCurrentTpl = NewTpl;
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//
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// If lowering below HIGH_LEVEL, make sure
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// interrupts are enabled
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//
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if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {
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CoreSetInterruptState (TRUE);
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}
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}
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