b2b1699910
QEMU hard codes the GPE0 registers at 0xafe0. Previously the code assumed that the GPE0 block would move when the PM Base Address of the PIIX4 PCI device was programmed. It appears QEMU does not emulate this behaviour of the PIIX4 PCI device. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Bei Guan <gbtju85@gmail.com> Reviewed-by: Bei Guan <gbtju85@gmail.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13276 6f19259b-4bc3-4df7-8a09-765794883524