91c38d4e94
Replace tabs by spaces for indentation to comply to EDK2 coding standards. Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf", "*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg, BeagleBoardPkg or Omap35xxPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
180 lines
7.0 KiB
C
Executable File
180 lines
7.0 KiB
C
Executable File
/** @file
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* Header defining the BeagleBoard constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __BEAGLEBOARD_PLATFORM_H__
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#define __BEAGLEBOARD_PLATFORM_H__
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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// SoC registers. L3 interconnects
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#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000
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#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000
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#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
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// SoC registers. L4 interconnects
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#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000
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#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000
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#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
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#if 0
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/*******************************************
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// Platform Memory Map
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*******************************************/
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// Can be NOR, DOC, DRAM, SRAM
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#define ARM_EB_REMAP_BASE 0x00000000
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#define ARM_EB_REMAP_SZ 0x04000000
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
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#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000
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#define ARM_EB_BOARD_PERIPH_BASE 0x10000000
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//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000
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// SMC
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#define ARM_EB_SMC_BASE 0x40000000
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#define ARM_EB_SMC_SZ 0x20000000
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// NOR Flash 1
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#define ARM_EB_SMB_NOR_BASE 0x40000000
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#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */
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// DOC Flash
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#define ARM_EB_SMB_DOC_BASE 0x44000000
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#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */
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// SRAM
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#define ARM_EB_SMB_SRAM_BASE 0x48000000
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#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */
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// USB, Ethernet, VRAM
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#define ARM_EB_SMB_PERIPH_BASE 0x4E000000
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//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000
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#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */
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// DRAM
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#define ARM_EB_DRAM_BASE 0x70000000
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#define ARM_EB_DRAM_SZ 0x10000000
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// Logic Tile
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#define ARM_EB_LOGIC_TILE_BASE 0xC0000000
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#define ARM_EB_LOGIC_TILE_SZ 0x40000000
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/*******************************************
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// Motherboard peripherals
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*******************************************/
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// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
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#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
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#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
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#define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050)
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#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
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#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
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#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
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#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
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#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
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// SP810 Controller
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#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
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// SYSTRCL Register
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#define ARM_EB_SYSCTRL 0x10001000
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// Uart0
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#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
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#define PL011_CONSOLE_UART_SPEED 115200
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// SP804 Timer Bases
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#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
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#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
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#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
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#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
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// PL301 RTC
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#define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000)
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// Dynamic Memory Controller Base
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#define ARM_EB_DMC_BASE 0x10018000
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// Static Memory Controller Base
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#define ARM_EB_SMC_CTRL_BASE 0x10080000
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#define PL111_CLCD_BASE 0x10020000
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//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption
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#define PL111_CLCD_VRAM_BASE 0x78000000
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#define ARM_EB_SYS_OSCCLK4 0x1000001C
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/*// System Configuration Controller register Base addresses
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//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000
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#define ARM_EB_SYS_CFGRW0_REG 0x100E2000
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#define ARM_EB_SYS_CFGRW1_REG 0x100E2004
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#define ARM_EB_SYS_CFGRW2_REG 0x100E2008
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#define ARM_EB_CFGRW1_REMAP_NOR0 0
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#define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)
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#define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)
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#define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)
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// PL301 Fast AXI Base Address
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#define ARM_EB_FAXI_BASE 0x100E9000
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// L2x0 Cache Controller Base Address
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//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
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// PL031 RTC - Other settings
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#define PL031_PPM_ACCURACY 300000000
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/*******************************************
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// Interrupt Map
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*******************************************/
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// Timer Interrupts
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#define TIMER01_INTERRUPT_NUM 34
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#define TIMER23_INTERRUPT_NUM 35
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/*******************************************
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// EFI Memory Map in Permanent Memory (DRAM)
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*******************************************/
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// This region is allocated at the bottom of the DRAM. It will be used
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// for fixed address allocations such as Vector Table
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#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
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// This region is the memory declared to PEI as permanent memory for PEI
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// and DXE. EFI stacks and heaps will be declared in this region.
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#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000
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#endif
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typedef enum {
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REVISION_XM,
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REVISION_UNKNOWN0,
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REVISION_UNKNOWN1,
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REVISION_UNKNOWN2,
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REVISION_UNKNOWN3,
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REVISION_C4,
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REVISION_C123,
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REVISION_AB,
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} BEAGLEBOARD_REVISION;
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#endif
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