0acd869796
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/** @file
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MSR Definitions.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
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**/
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#ifndef __FAM17_MSR_H__
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#define __FAM17_MSR_H__
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/**
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Secure Encrypted Virtualization (SEV) status register
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**/
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#define MSR_SEV_STATUS 0xc0010131
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/**
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MSR information returned for #MSR_SEV_STATUS
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
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///
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UINT32 SevBit:1;
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///
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/// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
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///
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UINT32 SevEsBit:1;
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UINT32 Reserved:30;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_SEV_STATUS_REGISTER;
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#endif
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