b5a572238d
This function allows platform to do any specific actions prior to the start the PEI phase. For instance, this function could be used by some platforms to initialize clocks that are required at the early stage of the PEI phase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14347 6f19259b-4bc3-4df7-8a09-765794883524
159 lines
4.8 KiB
NASM
159 lines
4.8 KiB
NASM
//
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// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <AutoGen.h>
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#include <Chipset/ArmV7.h>
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INCLUDE AsmMacroIoLib.inc
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IMPORT CEntryPoint
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IMPORT ArmPlatformIsPrimaryCore
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IMPORT ArmReadMpidr
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IMPORT ArmPlatformPeiBootAction
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IMPORT ArmPlatformStackSet
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EXPORT _ModuleEntryPoint
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PRESERVE8
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AREA PrePiCoreEntryPoint, CODE, READONLY
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StartupAddr DCD CEntryPoint
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_ModuleEntryPoint
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// Do early platform specific actions
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bl ArmPlatformPeiBootAction
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// Get ID of this CPU in Multicore system
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bl ArmReadMpidr
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// Keep a copy of the MpId register value
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mov r6, r0
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_SetSVCMode
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// Enter SVC mode, Disable FIQ and IRQ
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mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)
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msr CPSR_c, r1
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// Check if we can install the stack at the top of the System Memory or if we need
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// to install the stacks at the bottom of the Firmware Device (case the FD is located
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// at the top of the DRAM)
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_SetupStackPosition
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// Compute Top of System Memory
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LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)
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LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)
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sub r2, r2, #1
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add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize
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// Calculate Top of the Firmware Device
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LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)
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LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)
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sub r3, r3, #1
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add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize
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// UEFI Memory Size (stacks are allocated in this region)
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LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)
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//
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// Reserve the memory for the UEFI region (contain stacks on its top)
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//
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// Calculate how much space there is between the top of the Firmware and the Top of the System Memory
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subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop
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bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM
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cmp r0, r4
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bge _SetupStack
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// Case the top of stacks is the FdBaseAddress
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mov r1, r2
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_SetupStack
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// r1 contains the top of the stack (and the UEFI Memory)
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// Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment
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// one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the
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// top of the memory space)
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adds r7, r1, #1
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bcs _SetupOverflowStack
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_SetupAlignedStack
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mov r1, r7
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b _GetBaseUefiMemory
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_SetupOverflowStack
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// Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE
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// aligned (4KB)
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LoadConstantToReg (EFI_PAGE_MASK, r7)
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and r7, r7, r1
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sub r1, r1, r7
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_GetBaseUefiMemory
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// Calculate the Base of the UEFI Memory
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sub r7, r1, r4
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_GetStackBase
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// r1 = The top of the Mpcore Stacks
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// Stack for the primary core = PrimaryCoreStack
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LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)
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sub r8, r1, r2
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// Stack for the secondary core = Number of Cores - 1
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LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)
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sub r0, r0, #1
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)
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mul r1, r1, r0
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sub r8, r8, r1
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// r8 = The base of the MpCore Stacks (primary stack & secondary stacks)
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mov r0, r8
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mov r1, r6
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//ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)
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bl ArmPlatformStackSet
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// Is it the Primary Core ?
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mov r0, r6
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bl ArmPlatformIsPrimaryCore
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cmp r0, #1
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bne _PrepareArguments
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_ReserveGlobalVariable
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LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)
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// InitializePrimaryStack($GlobalVariableSize, $Tmp1)
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InitializePrimaryStack r0, r1
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_PrepareArguments
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mov r0, r6
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mov r1, r7
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mov r2, r8
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mov r3, sp
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// Move sec startup address into a data register
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// Ensure we're jumping to FV version of the code (not boot remapped alias)
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ldr r4, StartupAddr
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// Jump to PrePiCore C code
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// r0 = MpId
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// r1 = UefiMemoryBase
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// r2 = StacksBase
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// r3 = GlobalVariableBase
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blx r4
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_NeverReturn
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b _NeverReturn
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END
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