b7a97bfac5
Create a separate control flow for TDX BSP. TdxPostBuildPageTables will now only be called when running in TDX mode, so the TDX check in that function is not needed any more. No functional change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240301074402.98625-5-kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Oliver Steffen <osteffen@redhat.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Tom Lendacky <thomas.lendacky@amd.com> [lersek@redhat.com: turn the "Cc:" message headers from Gerd's on-list posting into "Cc:" tags in the commit message, in order to pacify "PatchCheck.py"]
151 lines
4.7 KiB
NASM
151 lines
4.7 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Sets the CR3 register for 64-bit paging
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2017 - 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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; common for all levels
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%define PAGE_PRESENT 0x01
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%define PAGE_READ_WRITE 0x02
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%define PAGE_USER_SUPERVISOR 0x04
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%define PAGE_WRITE_THROUGH 0x08
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%define PAGE_CACHE_DISABLE 0x010
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%define PAGE_ACCESSED 0x020
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%define PAGE_DIRTY 0x040
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%define PAGE_GLOBAL 0x0100
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; page table entries (level 1)
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%define PAGE_PTE_PAT 0x080
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; page directory entries (level 2+)
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%define PAGE_PDE_LARGEPAGE 0x080
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%define PAGE_PDE_PAT 0x01000
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%define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDE_LARGEPAGE_ATTR (PAGE_PDE_LARGEPAGE + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDE_DIRECTORY_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define TDX_BSP 1
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%define TDX_AP 2
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;
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; For OVMF, build some initial page tables at
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; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
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;
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; This range should match with PcdOvmfSecPageTablesSize which is
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; declared in the FDF files.
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;
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; At the end of PEI, the pages tables will be rebuilt into a
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; more permanent location by DxeIpl.
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;
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%macro ClearOvmfPageTables 0
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mov ecx, 6 * 0x1000 / 4
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xor eax, eax
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.clearPageTablesMemoryLoop:
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mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
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loop .clearPageTablesMemoryLoop
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%endmacro
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;
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; Create page tables for 4-level paging
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;
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; Argument: upper 32 bits of the page table entries
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;
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%macro CreatePageTables4Level 1
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (4)], %1
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1004)], %1
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x100C)], %1
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1014)], %1
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x101C)], %1
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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.pageTableEntriesLoop4Level:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_PDE_LARGEPAGE_ATTR
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mov dword[ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov dword[(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], %1
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loop .pageTableEntriesLoop4Level
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%endmacro
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;
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; Modified: EAX, EBX, ECX, EDX
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;
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SetCr3ForPageTables64:
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; Check the TDX features.
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; If it is TDX APs, then jump to SetCr3 directly.
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; In TD guest the initialization is done by BSP, including building
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; the page tables. APs will spin on until byte[TDX_WORK_AREA_PGTBL_READY]
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; is set.
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OneTimeCall CheckTdxFeaturesBeforeBuildPagetables
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cmp eax, TDX_BSP
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je TdxBspInit
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cmp eax, TDX_AP
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je SetCr3
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; Check whether the SEV is active and populate the SevEsWorkArea
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OneTimeCall CheckSevFeatures
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; If SEV is enabled, the C-bit position is always above 31.
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; The mask will be saved in the EDX and applied during the
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; the page table build below.
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OneTimeCall GetSevCBitMaskAbove31
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ClearOvmfPageTables
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CreatePageTables4Level edx
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; Clear the C-bit from the GHCB page if the SEV-ES is enabled.
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OneTimeCall SevClearPageEncMaskForGhcbPage
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jmp SetCr3
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TdxBspInit:
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;
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; TDX BSP workflow
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;
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ClearOvmfPageTables
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CreatePageTables4Level 0
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OneTimeCall TdxPostBuildPageTables
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jmp SetCr3
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SetCr3:
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;
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; Set CR3 now that the paging structures are available
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;
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mov eax, PT_ADDR (0)
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mov cr3, eax
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OneTimeCallRet SetCr3ForPageTables64
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