5f72e68c90
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions. Do not enable those features in CR4 if they are not supported. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17220 6f19259b-4bc3-4df7-8a09-765794883524
121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/** @file
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Supporting functions for X64 architecture.
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Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DebugAgent.h"
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/**
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Initialize IDT entries to support source level debug.
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**/
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VOID
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InitializeDebugIdt (
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VOID
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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UINTN InterruptHandler;
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IA32_DESCRIPTOR IdtDescriptor;
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UINTN Index;
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UINT16 CodeSegment;
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UINT32 RegEdx;
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AsmReadIdtr (&IdtDescriptor);
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//
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// Use current CS as the segment selector of interrupt gate in IDT
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//
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CodeSegment = AsmReadCs ();
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
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for (Index = 0; Index < 20; Index ++) {
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if (((PcdGet32 (PcdExceptionsIgnoredByDebugger) & ~(BIT1 | BIT3)) & (1 << Index)) != 0) {
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//
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// If the exception is masked to be reserved except for INT1 and INT3, skip it
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//
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continue;
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}
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InterruptHandler = (UINTN)&Exception0Handle + Index * ExceptionStubHeaderSize;
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IdtEntry[Index].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
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IdtEntry[Index].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
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IdtEntry[Index].Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
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IdtEntry[Index].Bits.Selector = CodeSegment;
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IdtEntry[Index].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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}
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InterruptHandler = (UINTN) &TimerInterruptHandle;
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.Selector = CodeSegment;
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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//
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// If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then
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// Set DE flag in CR4 to enable IO breakpoint
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//
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AsmCpuid (1, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT2) != 0) {
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AsmWriteCr4 (AsmReadCr4 () | BIT3);
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}
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}
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/**
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Retrieve exception handler from IDT table by ExceptionNum.
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@param[in] ExceptionNum Exception number
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@return Exception handler
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**/
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VOID *
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GetExceptionHandlerInIdtEntry (
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IN UINTN ExceptionNum
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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IA32_DESCRIPTOR IdtDescriptor;
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AsmReadIdtr (&IdtDescriptor);
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
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return (VOID *) (IdtEntry[ExceptionNum].Bits.OffsetLow |
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(((UINTN)IdtEntry[ExceptionNum].Bits.OffsetHigh) << 16) |
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(((UINTN)IdtEntry[ExceptionNum].Bits.OffsetUpper) << 32));
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}
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/**
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Set exception handler in IDT table by ExceptionNum.
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@param[in] ExceptionNum Exception number
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@param[in] ExceptionHandler Exception Handler to be set
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**/
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VOID
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SetExceptionHandlerInIdtEntry (
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IN UINTN ExceptionNum,
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IN VOID *ExceptionHandler
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)
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{
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IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
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IA32_DESCRIPTOR IdtDescriptor;
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AsmReadIdtr (&IdtDescriptor);
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IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
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IdtEntry[ExceptionNum].Bits.OffsetLow = (UINT16)(UINTN)ExceptionHandler;
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IdtEntry[ExceptionNum].Bits.OffsetHigh = (UINT16)((UINTN)ExceptionHandler >> 16);
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IdtEntry[ExceptionNum].Bits.OffsetUpper = (UINT32)((UINTN)ExceptionHandler >> 32);
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}
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