1a957f17bc
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3303 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
121 lines
4.2 KiB
C
121 lines
4.2 KiB
C
/** @file
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Public include file for Microcode library.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef MICROCODE_LIB_H_
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#define MICROCODE_LIB_H_
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#include <Register/Intel/Microcode.h>
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#include <Ppi/ShadowMicrocode.h>
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/**
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Get microcode update signature of currently loaded microcode update.
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@return Microcode signature.
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**/
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UINT32
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EFIAPI
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GetProcessorMicrocodeSignature (
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VOID
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);
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/**
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Get the processor signature and platform ID for current processor.
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@param MicrocodeCpuId Return the processor signature and platform ID.
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**/
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VOID
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EFIAPI
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GetProcessorMicrocodeCpuId (
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EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId
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);
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/**
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Return the total size of the microcode entry.
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Logic follows pseudo code in SDM as below:
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N = 512
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If (Update.DataSize != 00000000H)
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N = Update.TotalSize / 4
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If Microcode is NULL, then ASSERT.
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@param Microcode Pointer to the microcode entry.
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@return The microcode total size.
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**/
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UINT32
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EFIAPI
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GetMicrocodeLength (
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IN CPU_MICROCODE_HEADER *Microcode
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);
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/**
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Load the microcode to the processor.
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If Microcode is NULL, then ASSERT.
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@param Microcode Pointer to the microcode entry.
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**/
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VOID
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EFIAPI
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LoadMicrocode (
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IN CPU_MICROCODE_HEADER *Microcode
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);
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/**
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Detect whether specified processor can find matching microcode patch and load it.
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Microcode format is as below:
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+----------------------------------------+-------------------------------------------------+
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| CPU_MICROCODE_HEADER | |
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+----------------------------------------+ V
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| Update Data | CPU_MICROCODE_HEADER.Checksum
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+----------------------------------------+-------+ ^
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| CPU_MICROCODE_EXTENDED_TABLE_HEADER | | |
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+----------------------------------------+ V |
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| CPU_MICROCODE_EXTENDED_TABLE[0] | CPU_MICROCODE_EXTENDED_TABLE_HEADER.Checksum |
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| CPU_MICROCODE_EXTENDED_TABLE[1] | ^ |
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| ... | | |
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+----------------------------------------+-------+-----------------------------------------+
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There may by multiple CPU_MICROCODE_EXTENDED_TABLE in this format.
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The count of CPU_MICROCODE_EXTENDED_TABLE is indicated by ExtendedSignatureCount
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of CPU_MICROCODE_EXTENDED_TABLE_HEADER structure.
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If Microcode is NULL, then ASSERT.
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@param Microcode Pointer to a microcode entry.
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@param MicrocodeLength The total length of the microcode entry.
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@param MinimumRevision The microcode whose revision <= MinimumRevision is treated as invalid.
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Caller can supply value get from GetProcessorMicrocodeSignature() to check
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whether the microcode is newer than loaded one.
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Caller can supply 0 to treat any revision (except 0) microcode as valid.
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@param MicrocodeCpuIds Pointer to an array of processor signature and platform ID that represents
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a set of processors.
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Caller can supply zero-element array to skip the processor signature and
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platform ID check.
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@param MicrocodeCpuIdCount The number of elements in MicrocodeCpuIds.
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@param VerifyChecksum FALSE to skip all the checksum verifications.
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@retval TRUE The microcode is valid.
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@retval FALSE The microcode is invalid.
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**/
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BOOLEAN
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EFIAPI
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IsValidMicrocode (
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IN CPU_MICROCODE_HEADER *Microcode,
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IN UINTN MicrocodeLength,
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IN UINT32 MinimumRevision,
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IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds,
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IN UINTN MicrocodeCpuIdCount,
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IN BOOLEAN VerifyChecksum
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);
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#endif
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