9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/** @file
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Support for the PCI Express 3.0 standard.
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This header file may not define all structures. Please extend as required.
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Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIEXPRESS30_H_
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#define _PCIEXPRESS30_H_
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#include <IndustryStandard/PciExpress21.h>
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#pragma pack(1)
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1
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typedef union {
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struct {
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UINT32 PerformEqualization : 1;
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UINT32 LinkEqualizationRequestInterruptEnable : 1;
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UINT32 Reserved : 30;
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_LINK_CONTROL3;
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typedef union {
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struct {
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UINT16 DownstreamPortTransmitterPreset : 4;
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UINT16 DownstreamPortReceiverPresetHint : 3;
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UINT16 Reserved : 1;
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UINT16 UpstreamPortTransmitterPreset : 4;
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UINT16 UpstreamPortReceiverPresetHint : 3;
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UINT16 Reserved2 : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
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typedef struct {
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PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;
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UINT32 LaneErrorStatus;
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PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];
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} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
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#pragma pack()
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#endif
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