b75d1de536
In v1.5.0, QEMU's "pc" (i440fx) board gained a "CPU present bitmap" register block. In v2.0.0, this was extended to the "q35" board. In v2.7.0, a new (read/write) register interface was laid over the "CPU present bitmap", with an option for the guest to switch the register block to the new (a.k.a. modern) interface. Both interfaces are documented in "docs/specs/acpi_cpu_hotplug.txt" in the QEMU tree. Add macros for a minimal subset of the modern interface, just so we can count the possible CPUs (as opposed to boot CPUs) in a later patch in this series. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1515 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20191022221554.14963-3-lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/** @file
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Various register numbers and value bits based on the following publications:
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- Intel(R) datasheet 290549-001
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- Intel(R) datasheet 290562-001
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- Intel(R) datasheet 297654-006
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- Intel(R) datasheet 297738-017
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Copyright (C) 2015, Red Hat, Inc.
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Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __I440FX_PIIX4_H__
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#define __I440FX_PIIX4_H__
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#include <Library/PciLib.h>
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//
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// Host Bridge Device ID (DID) value for I440FX
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//
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#define INTEL_82441_DEVICE_ID 0x1237
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//
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// B/D/F/Type: 0/0/0/PCI
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//
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#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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#define PIIX4_PAM0 0x59
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#define PIIX4_PAM1 0x5A
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#define PIIX4_PAM2 0x5B
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#define PIIX4_PAM3 0x5C
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#define PIIX4_PAM4 0x5D
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#define PIIX4_PAM5 0x5E
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#define PIIX4_PAM6 0x5F
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//
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// B/D/F/Type: 0/1/3/PCI
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//
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#define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
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#define PIIX4_PMBA 0x40
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#define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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BIT10 | BIT9 | BIT8 | BIT7 | BIT6)
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#define PIIX4_PMREGMISC 0x80
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#define PIIX4_PMREGMISC_PMIOSE BIT0
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//
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// IO ports
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//
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#define PIIX4_CPU_HOTPLUG_BASE 0xAF00
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#endif
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