Files
system76-edk2/UefiCpuPkg/PiSmmCpuDxeSmm
Tan, Dun b670700ddf UefiCpuPkg/PiSmmCpuDxeSmm:Fix PF issue caused by smm page table code
When setting new page table pool to RO, only disable/enable WP when
Cr0.WP has been set to 1 to fix potential PF caused by b822be1a20
(UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanism).
With previous code, if someone want to modify the page table and
Cr0.WP has been cleared before modify page table, Cr0.WP may be set
to 1 again since new pool may be generated during this process
Then PF fault may happens.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
2023-01-03 06:41:11 +00:00
..
2022-12-19 06:12:56 +00:00
2021-12-07 17:24:28 +00:00
2021-12-07 17:24:28 +00:00