This is to add instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP_RAX in Nasm. The open CI is using NASM 2.14.02. CET instructions are supported since NASM 2.15.01. DB-encoded CET instructions need to be removed after open CI update to NASM 2.15.01. The BZ ticket is https://bugzilla.tianocore.org/show_bug.cgi?id=3227 . REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
35 lines
792 B
PHP
35 lines
792 B
PHP
;------------------------------------------------------------------------------
|
|
;
|
|
; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
|
; SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
;
|
|
; Abstract:
|
|
;
|
|
; This file provides macro definitions for NASM files.
|
|
;
|
|
;------------------------------------------------------------------------------
|
|
|
|
%macro SAVEPREVSSP 0
|
|
DB 0xF3, 0x0F, 0x01, 0xEA
|
|
%endmacro
|
|
|
|
%macro CLRSSBSY_EAX 0
|
|
DB 0x67, 0xF3, 0x0F, 0xAE, 0x30
|
|
%endmacro
|
|
|
|
%macro RSTORSSP_EAX 0
|
|
DB 0x67, 0xF3, 0x0F, 0x01, 0x28
|
|
%endmacro
|
|
|
|
%macro SETSSBSY 0
|
|
DB 0xF3, 0x0F, 0x01, 0xE8
|
|
%endmacro
|
|
|
|
%macro READSSP_EAX 0
|
|
DB 0xF3, 0x0F, 0x1E, 0xC8
|
|
%endmacro
|
|
|
|
%macro INCSSP_EAX 0
|
|
DB 0xF3, 0x0F, 0xAE, 0xE8
|
|
%endmacro
|